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| 型号： | LT8582IDKD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/36页 |
| 文件大小： | 0K |
| 描述： | IC REG MULTI CONFIG ADJ 3A 24DFN |
| 标准包装： | 52 |
| 类型： | 升压（升压），反相，回扫，Sepic |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 最高 42V |
| 输入电压： | 2.5 V ~ 22 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 2.5MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFDFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 24-DFN（7x4） |
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LT8582
APPLICATIONS INFORMATION
LAYOUT GUIDELINES FOR LT8582
General Layout Guidelines
? To improve thermal performance, solder the exposed
ground pad of the LT8582 to the ground plane, with
multiple vias in and around the pad connecting to ad-
ditional ground planes.
? A ground plane should be used under the switcher
circuitry to prevent interplane coupling and reduce
overall noise.
? High speed switching paths (see specific topology
below for more information) must be kept as short as
possible.
? The V C , FBX and R T components should be placed
as close to the LT8582 as possible, while being as far
away as practically possible from the switch node. The
ground for these components should be separated from
the switch current path.
? Place the bypass capacitors for the V IN pins (C VIN ) as
close as possible to the LT8582.
? Place the bypass capacitors for the inductors (C PWR )
as close as possible to the inductors.
Boost Topology Specific Layout Guidelines
? Keep length of loop (high speed switching path) gov-
erning switch, diode D1, output capacitor C OUT1 and
ground return as short as possible to minimize parasitic
inductive spikes during switching.
SEPIC Topology Specific Layout Guidelines
? Keep length of loop (high speed switching path) gov-
erning switch, flying capacitor C1, diode D1, output
capacitor C OUT1 and ground return as short as possible
to minimize parasitic inductive spikes during switching.
Inverting Topology Specific Layout Guidelines
? Keep ground return path from the cathode of D2
(to chip) separated from output capacitor C OUT3 ’s ground
return path (to chip) in order to minimize switching noise
coupling into the output. Notice the separate ground
return for D2’s cathode in Figure 8.
? Keep length of loop (high speed switching path) gov-
erning switch, flying capacitor C1 (in Figure 8), diode
D2 and ground return as short as possible to minimize
parasitic inductive spikes during switching.
? Bypass capacitors C PWR and C VIN may be combined
into a single bypass capacitor, C IN , if the input side of
the inductor can be close to the V IN pin of the LT8582.
8582f
16
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| LT8584IFE#PBF | 制造商:Linear Technology 功能描述:IC BATT CELL BALANCE 16TSSOP 制造商:Linear Technology 功能描述:BATTERY BALANCER, 2.5V-5.3V, TSSOP-16, Supply Voltage Min:2.5V, Supply Voltage M |
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| LT8610AHMSE#PBF | 制造商:Linear Technology 功能描述:IC REG BUCK SYNC ADJ 2.5A 16MSOP 制造商:Linear Technology 功能描述:SWITCHING REG, BUCK, ADJ, 2.2MHZ, MSOP16 制造商:Linear Technology 功能描述:SWITCHING REG, BUCK, ADJ, 2.2MHZ, MSOP16, Primary Input Voltage:42V, No. of Outp |
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