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| 型号： | LT8582IDKD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 25/36页 |
| 文件大小： | 0K |
| 描述： | IC REG MULTI CONFIG ADJ 3A 24DFN |
| 标准包装： | 52 |
| 类型： | 升压（升压），反相，回扫，Sepic |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 最高 42V |
| 输入电压： | 2.5 V ~ 22 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 2.5MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFDFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 24-DFN（7x4） |
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LT8582
APPENDIX
Maximum Inductance
Excessive inductance can reduce current ripple to levels
that are difficult for the current comparator (A4 in the
Block Diagram) to easily distinguish the peak current.
This causes duty cycle jitter and/or poor regulation. The
Note that these equations offer conservative results for
the required inductor current ratings. The current ratings
could be lower for applications with light loads and small
transients if the SS capacitor is sized appropriately to limit
inductor currents at start-up.
maximum inductance can be calculated by:
DIODE SELECTION
L MAX = IN
where
V – V CESAT
180mA
?
DC
f OSC
Schottky diodes, with their low forward voltage drops
and fast switching speeds, are recommended for use with
the LT8582. Choose a Schottky diode with low parasitic
capacitance to reduce reverse current spikes through the
I L _ PEAK = I LIM + IN
L MAX =L1 for boost topologies (see Figure 5)
L MAX = L1 = L2 for coupled dual inductor topologies
(see Figures 6 and 7)
L MAX = L1 || L2 for uncoupled dual inductor topologies
(see Figures 6 and 7)
Inductor Current Rating
Inductors must have a rating greater than their peak
operating current to prevent saturation, which results in
efficiency losses. The maximum inductor current (con-
sidering start-up, transient, and steady-state conditions)
is given by:
V ? T MIN _ PROP
L
where
I L_PEAK = Peak of Inductor Current in L1 for boost
topology, or peak of the sum of inductor
currents in L1 and L2 for dual inductor
topologies.
power switch of the LT8582. The Diodes Inc. PD3S230H
diode is a very good choice with a 30V reverse voltage
rating and an average forward current of 2A.
OUTPUT CAPACITOR SELECTION
Low ESR (equivalent series resistance) capacitors should
be used at the output to minimize the output ripple volt-
age. Multilayer ceramic capacitors are an excellent choice,
as they have an extremely low ESR and are available in
very small packages. X5R or X7R types are preferred,
as these retain their capacitance over wide voltage and
temperature ranges. A 10μF to 22μF output capacitor is
sufficient for most applications, but systems with very
low output currents may need only 2.2μF to 10μF. Always
use a capacitor with a sufficient voltage rating. Many
ceramic capacitors, particularly 0805 or 0603 case sizes,
have greatly reduced capacitance at the desired output
voltage. Tantalum polymer or OS-CON capacitors can be
used, but it is likely that these capacitors will occupy more
board area than ceramics and will have a higher ESR with
greater output ripple.
I LIM
= For hard saturation inductors, 5.4A when SWA
INPUT CAPACITOR SELECTION
and SWB are tied together, or 3A when only
SWA is being used. For soft saturation
inductors, 3.3A when SWA and SWB are tied
together, or 1.8A when only SWA is being
used.
T MIN_PROP = 55ns (propagation delay through the
current feedback loop)
Ceramic capacitors make a good choice for the input by-
pass capacitor and should be placed as close as possible
to the V IN pin of the chip as well as to the inductor con-
nected to the input of the power path. If it is not possible
to optimally place a single input capacitor, then use two
separate capacitors—use one at the V IN pin of the chip
(see the equation for C VIN in Table 1, Table 2 and Table 3)
8582f
25
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