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| 型号： | LTC1266IS#TR |
| 厂商： | Linear Technology |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM CM 16-SOIC |
| 标准包装： | 2,500 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 400kHz |
| 占空比： | 100% |
| 电源电压： | 3.5 V ~ 18 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 带卷 (TR) |
LTC1266
LTC1266-3.3/LTC1266-5
APPLICATIO S I FOR ATIO
operation, the DC supply current represents the lone (and
unavoidable) loss component which continues to become
a higher percentage as output current is reduced. As
expected the I 2 R losses dominate at high load currents.
Other losses including C IN and C OUT ESR dissipative
losses, MOSFET switching losses, Schottky conduction
losses during deadtime and inductor core losses, gener-
ally account for less than 2% total additional loss.
Design Example
As a design example, assume V IN = 5V (nominal),
V OUT = 3.3V, I MAX = 5A and f = 200kHz; R SENSE , C T and L
can immediately be calculated:
C IN will require an RMS current rating of at least 2.5A at
temperature and C OUT will require an ESR of 0.02 ? for
optimum efficiency.
Now allow V IN to drop to its minimum value. The minimum
V IN can be calculated from the maximum duty cycle and
voltage drop across the topside FET,
V OUT + I LOAD ? (R DS(ON) + R L + R SENSE )
V MIN = = 4.0V
D MAX
At this lower input voltage, the operating frequency de-
creases and the topside FET will be conducting most of the
time, causing the power dissipation to increase.
At dropout,
R SENSE = 100mV/5 = 0.02 ?
t OFF = (1/200kHz) ? [1 – (3.3/5)] = 1.7 μ s
f MIN =
1
t ON (MAX) + t OFF
= 16kHz
C T = 1.7 μ s/(1.3 ? 10 4 ) = 130pF
L MIN = 5.1 ? 10 5 ? 0.02 ? ? 130pF ? 3.3V = 5 μ H
Assume that the MOSFET dissipations are to be limited to
P T = P B = 2W.
If T A = 40 ° C and the thermal resistance of each MOSFET
is 50 ° C/ W, then the junction temperatures will be 140 ° C
and δ T = δ B = 0.60. The required R DS(ON) for each MOSFET
can now be calculated:
P T = I 2LOAD ? R DS(ON) ? (1 + δ T ) ? D MAX
This last step is necessary to assure that the power
dissipation and junction temperature of the topside FET
are not exceeded.
These last calculations assume that Power V IN is high
enough to keep the topside FET fully turned on at dropout,
as would be the case with the Figure 11circuit. If this isn’t
true (as with the Figure 1 circuit) the R DS(ON) will increase
TS R DS(ON) =
BS R DS(ON) =
5(2)
3.3(5) 2 (1.60)
5(2)
1.7(5) 2 (1.60)
= 0.076 ?
= 0.147 ?
which in turn increases V MIN and P T .
Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1266 adjustable version is used with an external
resistive divider from V OUT to V FB , Pin 10. The regulated
)
V OUT = 1.265 1 + R2
ThetopsideFETrequirementcanbemetbyanN-channel
Si9410DY which has an R DS(ON) of about 0.04 ? at
V GS = 5V. The bottom-side FET requirement is exceeded
by an Si9410DY. Note that the most stringent requirement
voltage is determined by:
R1
)
for the bottom-side MOSFET is with V OUT = 0 (i.e., short
circuit). During a continuous short circuit, the worst-case
dissipation rises to:
P B = I SC(AVG)2 ? R DS(ON) ? (1 + δ B )
With the 0.02 ? sense resistor, I SC(AVG) ≈ 6A will result,
increasing the 0.04 ? bottom-side FET dissipation to 2.3W.
To prevent stray pickup a 100pF capacitor is suggested
across R1 located close to the LTC1266.
For Figure 1 applications with V OUT below 2V, or when
R SENSE is moved to ground, the current sense comparator
inputs operate near ground. When the current comparator
is operated at less than 2V common mode, the off-time
increases approximately 40%, requiring the use of a
smaller timing capacitor C T .
15
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