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参数资料
| 型号： | LTC1407IMSE-1#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/26页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 3MSPS 10-MSOP |
| 标准包装： | 50 |
| 位数： | 12 |
| 采样率（每秒）： | 3M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 14mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 供应商设备封装： | 10-MSOP 裸露焊盘 |
| 包装： | 管件 |
| 输入数目和类型： | 4 个单端，单极；2 个差分，单极 |
| 产品目录页面： | 1346 (CN2011-ZH PDF) |
| 配用： | DC1082A-B-ND - BOARD SAR ADC LTC1407A DC1082A-A-ND - BOARD SAR ADC LTC1407A-1 |
LTC1407-1/LTC1407A-1
16
14071fb
APPLICATIONS INFORMATION
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC1407-1/LTC1407A-1, a printed
circuit board with ground plane is required. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track. If optimum phase match
between the inputs is desired, the length of the four input
wires of the two input channels should be kept matched.
But each pair of input wires to the two input channels
should be kept separated by a ground trace to avoid high
frequency crosstalk between channels.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD and VREF pins as shown in the
Block Diagram on the rst page of this data sheet. For
optimum performance, a 10μF surface mount tantalum
capacitor with a 0.1μF ceramic is recommended for the VDD
and VREF pins. Alternatively, 10μF ceramic chip capacitors
such as X5R or X7R may be used. The capacitors must be
located as close to the pins as possible. The traces con-
necting the pins and the bypass capacitors must be kept
short and should be made as wide as possible. The VDD
bypass capacitor returns to GND (Pin 6) and the VREF by-
pass capacitor returns to the Exposed Pad ground (Pin 11).
Care should be taken to place the 0.1μF VDD bypass ca-
pacitor as close to Pins 6 and 7 as possible.
Figure 7 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated
Figure 6a. The LT1819 Driving the LTC1407A-1 Differentially
Figure 6b. LTC1407-1 6MHz Sine Wave 4096 Point FFT Plot
with the LT1819 Driving the Inputs Differentially
Figure 7. Recommended Layout
–CH0 OR
–CH1
LTC1407A-1
+CH0 OR
+CH1
C1
47pF
R1
51Ω
C3
1μF
C5
0.1μF
5V
–5V
C4
1μF
R5
1k
1.5VCM
R3
499Ω
R4
499Ω
R6
1k
C2
47pF
R2
51Ω
C6
0.1μF
VIN
1.25VP-P
MAX
1407A F06a
–
+
U1
1/2 LT1819
–
+
U2
1/2 LT1819
FREQUENCY (Hz)
MAGNITUDE
(dB)
–60
–30
–20
14031 F06b
–70
–80
–120
–100
0
–10
–40
–50
–90
–110
0
371k
185k
556k
741k
1407-1 F07
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