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参数资料
| 型号： | LTC1407IMSE-1#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/26页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 3MSPS 10-MSOP |
| 标准包装： | 50 |
| 位数： | 12 |
| 采样率（每秒）： | 3M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 14mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 供应商设备封装： | 10-MSOP 裸露焊盘 |
| 包装： | 管件 |
| 输入数目和类型： | 4 个单端，单极；2 个差分，单极 |
| 产品目录页面： | 1346 (CN2011-ZH PDF) |
| 配用： | DC1082A-B-ND - BOARD SAR ADC LTC1407A DC1082A-A-ND - BOARD SAR ADC LTC1407A-1 |
LTC1407-1/LTC1407A-1
17
14071fb
APPLICATIONS INFORMATION
at the LTC1407-1/LTC1407A-1 Exposed Pad. The ground
return from the LTC1407-1/LTC1407A-1 Pin 6 to the power
supply should be low impedance for noise-free operation.
The Exposed Pad of the 10-lead MSE package is also tied
to Pin 6 and the LTC1407-1/LTC1407A-1 GND. The Exposed
Pad should be soldered on the PC board to reduce ground
connection inductance. Digital circuitry grounds must be
connected to the digital supply common.
POWER-DOWN MODES
Upon power-up, the LTC1407-1/LTC1407A-1 are initialized
to the active state and are ready for conversion. The nap
and sleep mode waveforms show the power-down modes
for the LTC1407-1/LTC1407A-1. The SCK and CONV inputs
control the power-down modes (see Timing Diagrams). Two
rising edges at CONV, without any intervening rising edges
at SCK, put the LTC1407-1/LTC1407A-1 in nap mode and
the power drain drops from 14mW to 6mW. The internal
reference remains powered in nap mode. One or more
rising edges at SCK wake up the LTC1407-1/LTC1407A-1
for service very quickly and CONV can start an accurate
conversion within a clock cycle.
Four rising edges at CONV, without any intervening rising
edges at SCK, put the LTC1407-1/LTC1407A-1 in sleep mode
and the power drain drops from 14mW to 10μW. To bring the
partoutofsleepmoderequiresoneormorerisingSCKedges
followed by a nap request. Then one or more rising edges
at SCK wake up the LTC1407-1/LTC1407A-1 for operation.
When nap mode is entered after sleep mode, the reference
that was shut down in sleep mode is reactivated.
The internal reference (VREF ) takes 2ms to slew and settle
with a 10μF load. Using sleep mode more frequently com-
promises the settled accuracy of the internal reference.
Note that for slower conversion rates, the nap and sleep
modes can be used for substantial reductions in power
consumption.
DIGITAL INTERFACE
The LTC1407-1/LTC1407A-1 have a 3-wire SPI (serial
protocol interface) interface. The SCK and CONV inputs
and SDO output implement this interface. The SCK and
CONV inputs accept swings from 3V logic and are TTL
compatible, if the logic swing does not exceed VDD. A de-
tailed description of the three serial port signals follows:
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subse-
quent rising edges at CONV are ignored by the LTC1407-1/
LTC1407A-1 until the following 32 SCK rising edges have
occurred. The duty cycle of CONV can be arbitrarily chosen
to be used as a frame sync signal for the processor serial
port.AsimpleapproachtogenerateCONVistocreateapulse
that is one SCK wide to drive the LTC1407-1/LTC1407A-1
and then buffer this signal to drive the frame sync input
of the processor serial port. It is good practice to drive the
LTC1407-1/LTC1407A-1 CONV input rst to avoid digital
noise interference during the sample-to-hold transition
triggered by CONV at the start of conversion. It is also good
practice to keep the width of the low portion of the CONV
signal greater than 15ns to avoid introducing glitches in
the front end of the ADC just before the sample-and-hold
goes into hold mode at the rising edge of CONV.
Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sinewaves
above 100kHz are sampled, the CONV signal must have
as little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement easily. The challenge is to generate a CONV
signal from this crystal clock without jitter corruption from
other digital circuits in the system. A clock divider and
any gates in the signal path from the crystal clock to the
CONV input should not share the same integrated circuit
with other parts of the system. As shown in the interface
circuit examples, the SCK and CONV inputs should be
driven rst, with digital buffers used to drive the serial port
interface. Also note that the master clock in the DSP may
already be corrupted with jitter, even if it comes directly
from the DSP crystal. Another problem with high speed
processor clocks is that they often use a low cost, low
speed crystal (i.e., 10MHz) to generate a fast, but jittery,
phase-locked-loop system clock (i.e., 40MHz). The jitter
in these PLL-generated high speed clocks can be several
nanoseconds. Note that if you choose to use the frame
sync signal generated by the DSP port, this signal will
have the same jitter of the DSP’s master clock.
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