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参数资料
| 型号： | LTC1667CG#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/24页 |
| 文件大小： | 0K |
| 描述： | IC D/A CONV 14BIT 50MSPS 28-SSOP |
| 标准包装： | 47 |
| 设置时间： | 20ns |
| 位数： | 14 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 双 ± |
| 功率耗散（最大）： | 180mW |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 管件 |
| 输出数目和类型： | 2 电流，单极 |
| 采样率（每秒）： | 50M |
| 产品目录页面： | 1352 (CN2011-ZH PDF) |
14
LTC1666/LTC1667/LTC1668
APPLICATIO S I FOR ATIO
WU
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Operating with Reduced Output Currents
The LTC1666/LTC1667/LTC1668 are specified to operate
with full-scale output current, IOUTFS, from the nominal
10mA down to 1mA. This can be useful to reduce power
dissipation or to adjust full-scale value. However, the DC
and AC accuracy is specified only at IOUTFS = 10mA, and
DC and AC accuracy will fall off significantly at lower IOUTFS
values. At IOUTFS = 1mA, the LTC1668 INL and DNL
typically degrade to the 14-bit to 13-bit level, compared to
16-bit to 15-bit typical accuracy at 10mA IOUTFS. Increas-
ing IOUTFS from 1mA, the accuracy improves rapidly,
roughly in proportion to 1/IOUTFS. Note that the AC perfor-
mance (SFDR) is affected much more by reduced IOUTFS
than it is by reduced digital amplitude (see Typical Perfor-
mance Characteristics). Therefore it is usually better to
make large gain adjustments digitally, keeping IOUTFS
equal to 10mA.
Output Configurations
Based on the specific application requirements, the
LTC1666/LTC1667/LTC1668 allow a choice of the best of
several output configurations. Voltage outputs can be
generated by external load resistors, transformer coupling
or with an op amp I-to-V converter. Single-ended DAC
output configurations use only one of the outputs, prefer-
ably IOUT A, to produce a single-ended voltage output.
Differential mode configurations use the difference be-
tween IOUT A and IOUT B to generate an output voltage,
VDIFF, as shown in equation 11. Differential mode gives
much better accuracy in most AC applications. Because
the DAC chip is the point of interface between the digital
input signals and the analog output, some small amount
of noise coupling to IOUT A and IOUT B is unavoidable. Most
of that digital noise is common mode and is canceled by
the differential mode circuit. Other significant digital noise
components can be modeled as VREF or IOUTFS noise. In
single-ended mode, IOUTFS noise is gone at zero scale and
is fully present at full scale. In differential mode, IOUTFS
noise is cancelled at midscale input, corresponding to zero
analog output. Many AC signals, including broadband and
multitone communications signals with high peak to aver-
age ratios, stay mostly near midscale.
Differential Transformer-Coupled Outputs
Differential transformer-coupled output configurations
usually give the best AC performance. An example is
shown in Figure 5. The advantages of transformer cou-
pling include excellent rejection of common mode distor-
tion and noise over a broad frequency range and conve-
nient differential-to-single-ended conversion with isola-
tion or level shifting. Also, as much as twice the power can
be delivered to the load, and impedance matching can be
accomplished by selecting the appropriate transformer
turns ratio. The center tap on the primary side of the
transformer is tied to ground to provide the DC current
path for IOUT A and IOUT B. For low distortion, the DC
average of the IOUT A and IOUT B currents must be exactly
equal to avoid biasing the core. This is especially impor-
tant for compact RF transformers with small cores. The
circuit in Figure 5 uses a Mini-Circuits T1-1T RF trans-
former with a 1:1 turns ratio. The load resistance on
IOUT A and IOUT B is equivalent to a single differential
resistor of 50
, and the 1:1 turns ratio means the output
impedance from the transformer is 50
. Note that the
load resistors are optional, and they dissipate half of the
output power. However, in lab environments or when
driving long transmission lines it is very desirable to have
a 50
output impedance. This could also be done with a
50
resistor at the transformer secondary, but putting
the load resistors on IOUT A and IOUT B is preferred since
it reduces the current through the transformer. At signal
frequencies lower than about 1MHz, the transformer core
size required to maintain low distortion gets larger, and at
some lower frequencies this becomes impractical.
Figure 5. Differential Transformer-Coupled Outputs
IOUT B
IOUT A
50
50
110
MINI-CIRCUITS
T1-1T
RLOAD
1666/7/8 F06
LTC1666/
LTC1667/
LTC1668
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| LTC1667IG#PBF | 功能描述:IC D/A CONV 14BIT 50MSPS 28-SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
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