参数资料
| 型号： | LTC2240CUP-12#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 15/30页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 170MSPS 64-QFN |
| 标准包装： | 40 |
| 位数： | 12 |
| 采样率（每秒）： | 170M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 638mW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-WFQFN 裸露焊盘 |
| 供应商设备封装： | 64-QFN（9x9） |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，双极 |
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LTC2240-12
22
224012fd
APPLICATIONS INFORMATION
In the CMOS output mode, OVDD can be powered with
any voltage up to 2.625V. OGND can be powered with any
voltage from GND up to 1V and must be less than OVDD.
The logic outputs will swing between OGND and OVDD.
In the LVDS output mode, OVDD should be connected to
a 2.5V supply and OGND should be connected to GND.
Output Enable
The outputs may be disabled with the output enable pin,
OE. In CMOS or LVDS output modes OE high disables all
data outputs including OF and CLKOUT. The data access
and bus relinquish times are too slow to allow the outputs
to be enabled and disabled during full speed operation.
The output Hi-Z state is intended for use during long
periods of inactivity.
The Hi-Z state is not a truly open circuit; the output pins
that make an LVDS output pair have a 20k resistance be-
tween them. Therefore in the CMOS output mode, adjacent
data bits will have 20k resistance in between them, even
in the Hi-Z state.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors
have to recharge and stabilize. Connecting SHDN to VDD
and OE to GND results in nap mode, which typically dis-
sipates 28mW. In nap mode, the on-chip reference circuit
is kept on, so that recovery from nap mode is faster than
that from sleep mode, typically taking 100 clock cycles. In
both sleep and nap mode all digital outputs are disabled
and enter the Hi-Z state.
GROUNDING AND BYPASSING
The LTC2240-12 requires a printed circuit board with a
clean unbroken ground plane. A multilayer board with
an internal ground plane is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
signal alongside an analog signal or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFHA, REFHB, REFLA and REFLB
pins. Bypass capacitors must be located as close to the
pins as possible. Of particular importance are the capaci-
tors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recommended. The 2.2μF capacitor between REFHA
and REFLA can be somewhat further away. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2240-12 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
HEAT TRANSFER
Most of the heat generated by the LTC2240-12 is trans-
ferred from the die through the bottom-side exposed pad
and package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad should
be soldered to a large grounded pad on the PC board. It
is critical that all ground pins are connected to a ground
plane of sufcient area.
Clock Sources for Undersampling
Undersampling is especially demanding on the clock
source and the higher the input frequency, the greater the
sensitivity to clock jitter or phase noise. A clock source that
degrades SNR of a full-scale signal by 1dB at 70MHz will
degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a canned oscillator from vendors such as Saronix or Vec-
tron can be placed close to the ADC and simply connected
directly to the ADC. If there is any distance to the ADC,
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2240CUP-12-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:12-Bit, 170Msps ADC |
| LTC2240CUP-12-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:12-Bit, 170Msps ADC |
| LTC2240IUP-10 | 制造商:LINER 制造商全称:Linear Technology 功能描述:10-Bit, 170Msps ADC |
| LTC2240IUP-10#PBF | 功能描述:IC ADC 10BIT 170MSPS 64-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| LTC2240IUP-10#TRPBF | 功能描述:IC ADC 10BIT 170MSPS 64-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
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