参数资料
| 型号： | LTC2242IUP-10#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/30页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 250MSPS 64-QFN |
| 标准包装： | 40 |
| 位数： | 10 |
| 采样率（每秒）： | 250M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 975mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-WFQFN 裸露焊盘 |
| 供应商设备封装： | 64-QFN（9x9） |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，双极 |
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LTC2242-10
23
224210fd
applicaTions inForMaTion
The lowest phase noise oscillators have single-ended si-
nusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
the filter and the ADC. If the circuit is sensitive to close-
in phase noise, the power supply for oscillators and any
buffersmustbeverystable,orpropagationdelayvariation
with supply will translate into phase noise. Even though
these clock sources may be regarded as digital devices,
do not operate them on a digital supply. If your clock is
also used to drive digital devices such as an FPGA, you
should locate the oscillator, and any clock fan-out devices
close to the ADC, and give the routing to the ADC prece-
dence. The clock signals to the FPGA should have series
termination at the driver to prevent high frequency noise
fromtheFPGAdisturbingthesubstrateoftheclockfan-out
device. If you use an FPGA as a programmable divider, you
must re-time the signal using the original oscillator, and
the re-timing flip-flop as well as the oscillator should be
close to the ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
fromdigitalsourcesbothradiated,aswellaspropagatedin
the waveguides that exist between the layers of multilayer
PCBs. The differential pairs must be close together and
distanced from other signals. The differential pair should
be guarded on both sides with copper distanced at least
3x the distance between the traces, and grounded with
vias no more than 1/4 inch apart.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2242IUP-10-TR | 制造商:LINER 制造商全称:Linear Technology 功能描述:10-Bit, 250Msps ADC |
| LTC2242IUP-10-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:10-Bit, 250Msps ADC |
| LTC2242IUP-12 | 制造商:Linear Technology 功能描述:ADC Single Pipelined 250Msps 12-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 12-bit, 250Msps ADC |
| LTC2242IUP-12#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 250Msps 12-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:Single ADC Pipelined 250Msps 12-bit Parallel/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 12BIT 250MSPS 64-QFN 制造商:Linear Technology 功能描述:A/D Converter (A-D) IC 制造商:Linear Technology 功能描述:IC, ADC, 12BIT, 250MSPS, QFN-64, Resolution (Bits):12bit, Sampling Rate:250MSPS, Supply Voltage Type:Single, Supply Voltage Min:2.375V, Supply Voltage Max:2.625V, Supply Current:285mA, Digital IC Case Style:QFN, No. of Pins:64 , RoHS Compliant: Yes 制造商:Linear Technology 功能描述:MS-ADC/High Speed, 12-bit, 250Msps ADC |
| LTC2242IUP-12#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 250Msps 12-bit Parallel/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 12BIT 250MSPS 64-QFN |
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