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| 型号： | LTC2251CUH#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10-BIT 125MSPS 3V 32-QFN |
| 标准包装： | 73 |
| 位数： | 10 |
| 采样率（每秒）： | 125M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 468mW |
| 电压电源： | 单电源 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，双极; 1 个差分，双极 |
| 产品目录页面： | 1349 (CN2011-ZH PDF) |
LTC2251/LTC2250
17
22510fa
a transformer provides no incremental contribution to
phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz
will degrade the SNR compared to the transformer solu-
tion. The nature of the received signals also has a large
bearing on how much SNR degradation will be experi-
enced. For high crest factor signals such as WCDMA or
OFDM, where the nominal power level must be at least 6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
The transformer shown in the example may be terminated
with the appropriate termination for the signaling in use.
The use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed to
ground through a capacitor close to the ADC if the differ-
ential signals originate on a different plane. The use of a
capacitor at the input may result in peaking, and depend-
ing on transmission line length may require a 10
to 20
ohm series resistor to act as both a low pass filter for high
frequency noise that may be induced into the clock line by
neighboring digital signals, as well as a damping mecha-
nism for reflections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2251/LTC2250
is 125Msps (LTC2251) and 105Msps (LTC2250). The
lower limit of the LTC2251/LTC2250 sample rate is deter-
mined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum
operating frequency for the LTC2251/LTC2250 is 1Msps.
Clock Duty Cycle Stabilizer
An optional clock duty cycle stabilizer circuit ensures high
performance even if the input clock has a non 50% duty
cycle. Using the clock duty cycle stabilizer is recom-
mended for most applications. To use the clock duty cycle
stabilizer, the MODE pin should be connected to 1/3VDD or
2/3VDD using external resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and the
APPLICATIO S I FOR ATIO
WU
U
internal falling edge is generated by a phase-locked loop.
The input clock duty cycle can vary from 40% to 60% and
the clock duty cycle stabilizer will maintain a constant
50% internal duty cycle. If the clock is turned off for a long
period of time, the duty cycle stabilizer circuit will require
a hundred clock cycles for the PLL to lock onto the input
clock.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
to make the sampling clock have a 50% (
±5%) duty cycle.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
D9 – D0
(2V Range)
OF
(Offset Binary)
(2’s Complement)
>+1.000000V
1
11 1111 1111
01 1111 1111
+0.998047V
0
11 1111 1111
01 1111 1111
+0.996094V
0
11 1111 1110
01 1111 1110
+0.001953V
0
10 0000 0001
00 0000 0001
0.000000V
0
10 0000 0000
00 0000 0000
–0.001953V
0
01 1111 1111
11 1111 1111
–0.003906V
0
01 1111 1110
11 1111 1110
–0.998047V
0
00 0000 0001
10 0000 0001
–1.000000V
0
00 0000 0000
10 0000 0000
<–1.000000V
1
00 0000 0000
10 0000 0000
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, iso-
lated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50
to external
circuitry and may eliminate the need for external damping
resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2251/LTC2250 should drive a
minimal capacitive load to avoid possible interaction
between the digital outputs and sensitive input circuitry.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC2251IUH | 制造商:LINER 制造商全称:Linear Technology 功能描述:10-Bit, 125/105Msps Low Noise 3V ADCs |
| LTC2251IUH#PBF | 功能描述:IC ADC 10-BIT 125MSPS 3V 32-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| LTC2251IUH#TRPBF | 功能描述:IC ADC 10BIT 125MSPS 3V 32-QFN RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
| LTC2252 | 制造商:LINER 制造商全称:Linear Technology 功能描述:14-Bit, 125/105Msps Low Power 3V ADCs |
| LTC2252CUH | 制造商:Linear Technology 功能描述:Single ADC Pipelined 105Msps 12-bit Parallel 32-Pin QFN EP |
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