参数资料
型号: LTC2272IUJ#TR
厂商: LINEAR TECHNOLOGY CORP
元件分类: ADC
英文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40
封装: 6 X 6 MM, PLASTIC, QFN-40
文件页数: 8/44页
文件大小: 767K
代理商: LTC2272IUJ#TR
LTC2273/LTC2272
16
22732fa
FAM (Pin 31): Frame Alignment Monitor Enable. A high
level enables the substitution of predetermined data at the
end of the frame with a K28.7 symbol for frame alignment
monitoring.
PAT0 (Pin 32): Pattern Select Bit0. Use with PAT1 to select
a test pattern for the serial interface.
PAT1 (Pin 33): Pattern Select Bit1. Use with PAT0 to select
a test pattern for the serial interface.
SCRAM (Pin 34): Enable Data Scrambling. A high level on
this pin will apply the polynomial 1 + x14 + x15 in scram-
bling each ADC data sample. The scrambling takes place
before the 8B/10B encoding.
PGA (Pin 35): Programmable Gain Amplier Control
Pin. Low selects a front-end gain of 1, input range of
2.25VP-P. High selects a front-end gain of 1.5, input range
of 1.5VP-P.
MSBINV (Pin 36): Invert the MSB. A high level will invert
the MSB to enable the 2’s compliment format.
SENSE (Pin 38): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
VCM (Pin 39): 1.25V Output. Optimum voltage for input
common mode. Must be bypassed to ground with a
minimum of 2.2μF. Ceramic chip capacitors are recom-
mended.
GND (Exposed Pad) (Pin 41): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
PIN FUNCTIONS
相关PDF资料
PDF描述
LTC2273IUJ#TR 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40
LTC2273IUJ 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40
LTC2274CUJ#TR 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40
LTC2274CUJ 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40
LTC2274IUJ#TR 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40
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