参数资料
型号: LTC3388IDD-1#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: 0.21 A SWITCHING REGULATOR, PDSO10
封装: 3 X 3 MM, LEAD FREE, PLASTIC, MO-229WEED-2, DFN-10
文件页数: 4/20页
文件大小: 282K
代理商: LTC3388IDD-1#PBF
LTC3388-1/LTC3388-3
12
338813f
OPERATION
output is in regulation. The PGOOD pin will remain Hi-Z
until VOUT falls to 92% of the desired regulation voltage.
Additionally, if PGOOD is high and VIN falls below the
UVLO falling threshold, PGOOD will remain high until
VOUT falls to 92% of the desired regulation point. This
allows output energy to be used even if the input is lost.
Figure 2 shows the behavior for VOUT = 1.8V and a 10μA
load. At t = 2s VIN becomes high impedance and is dis-
charged by the quiescent current of the LTC3388-1 and
through servicing VOUT. VIN crosses UVLO falling but
PGOOD remains high until VOUT decreases to 92% of the
desired regulation point.
This scenario is likely for cases in which the selected
output voltage is below the UVLO falling threshold. If the
input becomes high impedance and begins to fall it will
be supported by the output through the body diode of
the PMOS switch. For a high enough output voltage the
part will not necessarily enter UVLO while VOUT remains
PGOOD. This is always true for the output voltages avail-
able on the LTC3388-3.
The D0/D1 inputs can be switched while in regulation as
shown in Figure 3. If VOUT is programmed to a voltage with
a PGOOD falling threshold above the old VOUT, PGOOD will
transition low until the new regulation point is reached.
When VOUT is programmed to a lower voltage, PGOOD
will remain high through the transition.
The PGOOD pin is designed to drive a microprocessor or
other chip I/O and is not intended to drive higher current
loads such as an LED.
Figure 2. PGOOD Operation During Transition to UVLO
Figure 3. PGOOD Operation During D0/D1 Transition
Four selectable voltages are available by tying the output
select bits, D0 and D1, to GND or VIN2. Table 1 shows the
four D0/D1 codes and their corresponding output voltages
as well as the difference in output voltages between the
LTC3388-1 and LTC3388-3.
Table 1. LTC3388-1/LTC3388-3 Output Voltage Selection
D1
D0
VOUT
VOUT Quiescent Current (IVOUT)
0
1.2V/2.8V
28nA/66nA
0
1
1.5V/3.0V
36nA/72nA
1
0
1.8V/3.3V
43nA/78nA
1
2.5V/5.0V
60nA/120nA
The internal feedback network draws a small amount of
current from VOUT as listed in Table 1.
Dropout Operation
When the input supply voltage decreases towards the
output voltage, the rate of change of inductor current
decreases, reducing the switching frequency of the cur-
rent bursts. Further reduction in input supply voltage will
eventually cause the PMOS to be turned on 100%, i.e.,
DC. The output voltage will then be determined by the
input voltage minus the voltage drop across the PMOS
and the inductor.
Power Good Comparator
A power good comparator causes the PGOOD pin to
go Hi-Z the first time the converter reaches the sleep
threshold of the programmed VOUT, signaling that the
TIME (sec)
0
VOL
TAGE
(V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
338813 F02
8
6
4
210
VOUT
VIN
VIN = UVLO FALLING
PGOOD
CIN = 22μF, COUT = 100μF, ILOAD = 10μA
TIME (ms)
0
V
OUT
VOL
TAGE
(V)
6
5
4
3
2
1
0
338813 F03
8
6
4
210
18
16
14
12
20
VOUT
COUT = 100μF, ILOAD = 50mA
PGOOD = LOGIC 1
D1=D0=0
D1=D0=1
D1=D0=0
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