参数资料
型号: LTC3411IMS#TRPBF
厂商: Linear Technology
文件页数: 14/24页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 10MSOP
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 5 V
输入电压: 2.63 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 1MHz
电流 - 输出: 1.25A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 带卷 (TR)
供应商设备封装: 10-MSOP
LTC3411
APPLICATIONS INFORMATION
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.
The I TH external components shown in the Figure 1 circuit
will provide an adequate starting point for most applica-
tions. The series R-C ?lter sets the dominant pole-zero
loop compensation. The values can be modi?ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the ?nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1μs
to 10μs will produce output voltage and I TH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V OUT im-
mediately shifts by an amount equal to Δ I LOAD ? ESR, where
ESR is the effective series resistance of C OUT . Δ I LOAD also
begins to charge or discharge C OUT generating a feedback
error signal used by the regulator to return V OUT to its
steady-state value. During this recovery time, V OUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C.
If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, a feedforward capacitor
C F can be added to improve the high frequency response,
as shown in Figure 5. Capacitor C F provides phase lead by
creating a high frequency zero with R2 which improves
the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage V IN drops toward V OUT , the load step capability
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta or single inductor, positive buck/boost.
V IN
2.5V
TO 5.5V
C6
+
C IN
R6
SV IN
PV IN
PGOOD
R5
PGOOD
D1
PGND
PGND
C8
SGND
LTC3411
SYNC/MODE
SW
L1
OPTIONAL
C F
+
C OUT
C5
V OUT
I TH
V FB
SGND
C ITH
R C
SGND PGND
SHDN/R T
R1
R2
PGND
PGND
C C
R T
SGND
SGND
GND
SGND SGND
3411 F05
Figure 5. LTC3411 General Schematic
3411fb
14
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