参数资料
型号: LTC3417AIFE-1#TRPBF
厂商: Linear Technology
文件页数: 13/20页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ DL 20TSSOP
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.8 V ~ 5 V
输入电压: 2.25 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 1.5MHz,600kHz ~ 4MHz
电流 - 输出: 1A,1.5A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 20-TSSOP-EP
LTC3417A-1
APPLICATIONS INFORMATION
V RUN
2V/DIV
V OUT
1V/DIV
I L
1A/DIV
The LTC3417A-1 can be synchronized to an external clock
signal by the SYNC/MODE pin. The internal oscillator fre-
quency should be set to 20% lower than the external clock
frequency to ensure adequate slope compensation, since
slope compensation is derived from the internal oscillator.
During synchronization, the mode is set to pulse skipping
and the top switch turn-on is synchronized to the rising
edge of the external clock.
V IN = 3.6V
V OUT = 1.8V
R L = 0.9Ω
200μs/DIV
3417A-1 F02
When using an external clock, with the PHASE pin low, the
switching of the two channels occur at the edges of the
Figure 2. Digital Soft-Start OUT1
Soft-Start
Soft-start reduces surge currents from V IN by gradu-
ally increasing the peak inductor current. Power supply
sequencing can also be accomplished by controlling the
I TH pin. The LTC3417A-1 has an internal digital soft-start
for each regulator output, which steps up a clamp on
I TH over 1024 clock cycles, as can be seen in Figures 2
and 3. As the voltage on I TH ramps through its operating
range, the internal peak current limit is also ramped at a
proportional linear rate.
Mode Selection
The SYNC/MODE pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect-
ing this pin to V IN enables Burst Mode operation for both
regulators, which provides the best low current ef?ciency
at the cost of a higher output voltage ripple. When SYNC/
MODE is connected to ground, pulse skipping operation
is selected for both regulators, which provides the low-
est output voltage and current ripple at the cost of low
current ef?ciency. Applying a voltage that is more than
1V from either supply results in forced continuous mode
external clock. A 50% duty cycle will therefore produce
180 ° out-of-phase operation.
Checking Transient Response
The I TH pin compensation allows the transient response
to be optimized for a wide range of loads and output
capacitors. The availability of the I TH pin not only allows
optimization of the control loop behavior, but also pro-
vides a DC coupled and AC ?lited closed-loop response
test point. The DC step, rise time, and settling at this test
point truly re?ects the closed-loop response. Assuming a
predominantly second order system, phase margin and/or
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated using the percentage of overshoot seen at this
pin or by examining the rise time at this pin.
V RUN
2V/DIV
V OUT
1V/DIV
I L
0.5A/DIV
for both regulators, which creates a ?xed output ripple
and allows the sinking of some current (about 1/2 Δ I L ).
Since the switching noise is constant in this mode, it is
V IN = 3.6V
V OUT = 2.5V
R L = 2Ω
200μs/DIV
3417A-1 F03
also the easiest to ?lter out. In many cases, the output
voltage can be simply connected to the SYNC/MODE pin,
Figure 3. Digital Soft-Start OUT2
selecting the forced continuous mode except at start-up.
3417a1fa
13
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