参数资料
型号: LTC3421EUF#TRPBF
厂商: Linear Technology
文件页数: 12/16页
文件大小: 0K
描述: IC REG BOOST SYNC ADJ 1.5A 24QFN
标准包装: 2,500
类型: 升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 2.4 V ~ 5.25 V
输入电压: 0.5 V ~ 4.5 V
PWM 型: 电流模式,混合
频率 - 开关: 100kHz ~ 3MHz
电流 - 输出: 1.5A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 24-QFN 裸露焊盘(4x4)
LTC3421
APPLICATIO S I FOR ATIO
Output Capacitor Selection
The output voltage ripple has two components to it. The
bulk value of the capacitor is set to reduce the ripple due
to charge into the capacitor each cycle. The maximum
ripple due to charge is given by:
Operating Frequency Selection
There are several considerations in selecting the operating
frequency of the converter. The first is, which are the sen-
sitive frequency bands that cannot tolerate any spectral
noise? The second consideration is the physical size of the
V RBULK =
I P ? V IN
C OUT ? V OUT ? f
converter. As the operating frequency goes up, the induc-
tor and filter capacitors go down in value and size. The trade
off is in efficiency since the switching losses due to gate
where I P = peak inductor current.
The ESR (equivalent series resistance) is usually the most
dominant factor for ripple in most power converters. The
ripple due to capacitor ESR is simply given by:
V RCESR = I P ? C ESR
where C ESR = capacitor series resistance.
Low ESR capacitors should be used to minimize output
voltage ripple. For surface mount applications, AVX TPS
series tantalum capacitors, Sanyo POSCAP or Taiyo Yuden
charge are going up proportional with frequency.
Another operating frequency consideration is whether the
application can allow “pulse skipping.” In this mode, the
minimum on time of the converter cannot support the duty
cycle, so the converter ripple will go up and there will be
a low frequency component of the output ripple. In many
applications where physical size is the main criterion,
running the converter in this mode is acceptable. In appli-
cations where it is preferred not to enter this mode, the
maximum operating frequency is given by:
ceramic capacitors are recommended. For through-hole
applications, Sanyo OS-CON capacitors offer low ESR in a
small package size.
f MAX _ NOSKIP =
V OUT ? t ON ( MIN )
V OUT – V IN
Hz
In some layouts it may be necessary to place a 1 μ F low ESR
ceramic capacitor as close to the V OUT and GND pins as
possible.
Input Capacitor Selection
The input filter capacitor reduces peak currents drawn
from the input source and reduces input switching noise.
Since the IC can operate at voltages below 0.5V once the
output is regulated, the demand on the input capacitor is
much less. In most applications 1 μ F per amp of peak input
current is recommended. Taiyo Yuden offers very low ESR
ceramic capacitors, for example the 1 μ F in a 0603 case
(JMK107BJ105MA).
where t ON(MIN) = minimum on time = 120ns.
Thermal Considerations
To deliver the power that the LTC3421 is capable of, it is
imperative that a good thermal path be provided to
dissipate the heat generated within the package. This can
be accomplished by taking advantage of the large thermal
pad on the underside of the IC. It is recommended that mul-
tiple vias in the printed circuit board be used to conduct
heat away from the IC and into a copper plane with as much
area as possible. In the event that the junction tempera-
ture gets too high, the peak current limit will automatically
be decreased. If the junction temperature continues to rise,
Table 2. Capacitor Vendor Information
SUPPLIER PHONE FAX
WEB SITE
the part will go into thermal shutdown, and all switching
will stop until the temperature drops.
AVX
Sanyo
TDK
Murata
(803) 448-9411
(619) 661-6322
(847) 803-6100
USA:
(803) 448-1943
(619) 661-1055
(847) 803-6296
USA:
www.avxcorp.com
www.sanyovideo.com
www.component.tdk.com
www.murata.com
V IN > V OUT Operation
The LTC3421 will maintain voltage regulation when the
input voltage is above the output voltage. This is achieved
(814) 237-1431
(800) 831-9172
Taiyo Yuden (408) 573-4150
(814) 238-0490
(408) 573-4159 www.t-yuden.com
by terminating the switching on the synchronous PMOS
and applying V IN statically on the gate. This will ensure the
3421f
12
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