参数资料
| 型号： | LTC3424EMS#TR |
| 厂商： | Linear Technology |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC REG BOOST SYNC ADJ 2A 10MSOP |
| 标准包装： | 2,500 |
| 类型： | 升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.5 V ~ 5.5 V |
| 输入电压： | 0.5 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 3MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-MSOP |
| 其它名称： | LTC3424EMSTR |
LTC3423/LTC3424
APPLICATIO S I FOR ATIO
The inductor current ripple is typically set to 20% to 40%
of the maximum inductor current.
For high efficiency, choose an inductor with a high fre-
quency core material, such as ferrite, to reduce core
losses. The inductor should have low ESR (equivalent
series resistance) to reduce the I 2 R losses and must be
able to handle the peak inductor current at full load without
saturating. Molded chokes or chip inductors usually do
not have enough core to support the peak inductor cur-
rents in the 1A to 2A region. To minimize radiated noise,
use a toroid, pot core or shielded bobbin inductor. See
Table 1 for a list of component suppliers.
Table 1. Inductor Vendor Information
where
I L = Average Inductor Current
I P = Peak Inductor Current
The ESR is usually the most dominant factor for ripple in
most power converters. The ripple due to capacitor ESR is
simply given by:
VR CESR = I P ? R ESR Volts
where
R ESR = Capacitor Series Resistance
Low ESR capacitors should be used to minimize output
voltage ripple. For surface mount applications, AVX TPS
SUPPLIER
Coilcraft
Coiltronics
Murata
PHONE
(847) 639-6400
(516) 241-7876
(814) 237-1431
(800) 831-9172
FAX
(847) 639-1469
(516) 241-9339
(814) 238-0490
WEBSITE
www.coilcraft.com
www.coiltronics.com
www.murata.com
series tantalum capacitors and Sanyo POSCAP or Taiyo-
Yuden ceramic capacitors are recommended. For through-
hole applications Sanyo OS-CON capacitors offer low ESR
in a small package size. See Table 2 for a list of component
suppliers.
Sumida
USA: (847) 956-0666 (847) 956-0702
Japan: 81-3-3607-5111 81-3-3607-5144
www.japanlink.com
sumida
In some layouts it may be required to place a 1 μ F low ESR
capacitor as close to the V OUT and GND pins as possible.
Table 2. Capacitor Vendor Information
SUPPLIER
PHONE
FAX
WEBSITE
R t
MODE
SHDN
V C
AVX
(803) 448-9411
(803) 448-1943
www.avxcorp.com
V IN
SW
GND
FB
V OUT
V DD
V DD IN
2.7V
TO 5.5V
Sanyo
Taiyo Yuden
(619) 661-6322
(408) 573-4150
(619) 661-1055
(408) 573-4159
www.sanyovideo.com
www.t-yuden.com
Input Capacitor Selection
V OUT
3423/24 F01
Figure 1. Recommended Component Placement. Traces
Carrying High Current Are Direct. Trace Area FB and V C Pins
Are Kept Low. Lead Length to Battery Should be Kept Short
Output Capacitor Selection
The output voltage ripple has several components. The
bulk value of the capacitor is set to reduce the ripple due
to charge into the capacitor each cycle. The max ripple due
to charge is given by:
The input filter capacitor reduces peak currents drawn from
the input source and reduces input switching noise. In most
applications a 3.3 μ F is sufficient.
Output Diode
The Schottky diode across the synchronous PMOS switch
is not required, but provides a lower drop during the break-
before-make time (typically 20ns) of the NMOS to PMOS
transition. The addition of the Schottky diode will improve
peak efficiency (see graph “Efficiency Loss Without
Schottky vs Frequency”). Use of a Schottky diode such as
a MBRM120T3, 1N5817 or equivalent. Since slow recov-
VR BULK =
I L ? V IN ( V OUT – V IN )
C OUT ? V OUT ? V OUT ? f
Volts
ery times will compromise efficiency, do not use ordinary
rectifier diodes.
34234f
8
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