参数资料
型号: LTC3538EDCB#TRPBF
厂商: Linear Technology
文件页数: 11/16页
文件大小: 0K
描述: IC REG BUCK BOOST SYNC ADJ 8DFN
标准包装: 2,500
类型: 降压(降压),升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 1.8 V ~ 5.25 V
输入电压: 2.4 V ~ 5.5 V
频率 - 开关: 1MHz
电流 - 输出: 800mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 8-DFN(3x2)
LTC3538
OPERATION
Since the output current is discontinuous in boost mode,
the ripple in this mode will generally be much larger than
the magnitude of the ripple in buck mode.
Minimizing solution size is usually a priority. Please be
aware that ceramic capacitors can exhibit a signi?cant
reduction in effective capacitance when a bias is applied.
The capacitors exhibiting the highest reduction are those
packaged in the smallest case size.
Input Capacitor Selection
Since V IN is the supply voltage for the IC it is recommended
to place at least a 4.7μF, low ESR ceramic bypass capaci-
tor close to V IN and GND. It is also important to minimize
any stray resistance from the converter to the battery or
other power source.
Optional Schottky Diodes
Schottky diodes across the synchronous switches B and
D are not required, but do provide a lower drop during the
break-before-make time (typically 15ns), thus improving
ef?ciency. Use a surface mount Schottky diode such as an
MBRM120T3 or equivalent. Do not use ordinary recti?er
diodes since their slow recovery times will compromise
ef?ciency.
Table 2. Capacitor Vendor Information
SUPPLIER PHONE FAX WEB SITE
AVX (803) 448-9411 (803) 448-1943 www.avxcorp.com
Sanyo (619) 661-6322 (619) 661-1055 www.sanyovideo.com
importantly, leakage and parasitic capacitance need to
be minimized. During start-up, 1.5μA is typically sourced
from V C . The leakage of an external pull-down device and
compensation components tied to V C , must therefore be
minimized to ensure proper start-up. Capacitance from
the pull-down device should also be minimized as it can
affect converter stability. An N-channel MOSFET such as
the FDV301N or similar is recommended if an external
discrete N-channel MOSFET is needed.
PCB Layout Considerations
The LTC3538 switches large currents at high frequencies.
Special care should be given to the PCB layout to ensure
stable, noise-free operation. Figure 3 depicts the recom-
mended PCB layout to be utilized for the LTC3538. A few
key guidelines follow:
1. All circulating current paths should be kept as short as
possible. This can be accomplished by keeping the routes
to all components (except the FB divider network) in
Figure 3 as short and as wide as possible. Capacitor ground
connections should via down to the ground plane in the
shortest route possible. The bypass capacitor on V IN should
be placed as close to the IC as possible and should have
the shortest possible paths to ground.
2. The small signal ground pad (GND) should have a single
point connection to the power ground. A convenient way
to achieve this is to short this pin directly to the Exposed
Pad as shown in Figure 3.
Taiyo
Yuden
TDK
(408) 573-4150 (408) 573-4159 www.t-yuden.com
(847) 803-6100 (847) 803-6296 www.component.tdk.com
3. The components in bold and their connections should
all be placed over a complete ground plane.
4. To prevent large circulating currents from disrupting
the output voltage sensing, the ground for the resistor
Shutdown MOSFET Selection
A discrete external N-channel MOSFET, open-drain pull-
down device or other suitable means can be used to put
the part in shutdown by pulling V C below 0.25V. Since
the error ampli?er sources 13μA typically when active
and 1.5μA in shutdown, a relatively high resistance pull-
divider should be returned directly to the small signal
ground (GND) as shown.
5. Use of vias in the attach pad will enhance the thermal
environment of the converter especially if the vias extend
to a ground plane region on the exposed bottom surface
of the PCB.
down device can be used to pull V C below 0.25V. More
3538fb
11
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