参数资料
型号: LTC3538EDCB#TRPBF
厂商: Linear Technology
文件页数: 12/16页
文件大小: 0K
描述: IC REG BUCK BOOST SYNC ADJ 8DFN
标准包装: 2,500
类型: 降压(降压),升压(升压)
输出类型: 可调式
输出数: 1
输出电压: 1.8 V ~ 5.25 V
输入电压: 2.4 V ~ 5.5 V
频率 - 开关: 1MHz
电流 - 输出: 800mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 8-DFN(3x2)
LTC3538
OPERATION
? FILTER _ POLE =
V IN
2 ? V OUT ? π ? L ? C OUT
Hz
(in boost mode)
1
8
FB
2
V IN
7
where L is in Henries and C OUT is in Farads.
The output ?lter zero is given by:
V C
3
SW1
6
? FILTER _ ZERO =
1
2 ? π ? R ESR ? C OUT
Hz
GND
SW2
4
BURST
5
V OUT
V OUT
where R ESR is the equivalent series resistance of the
output capacitor.
A troublesome feature in boost mode is the right-half plane
zero (RHP), given by:
VIA TO GND PLANE
3538 F03
? RHPZ =
V IN 2
2 ? π ? I OUT ? L ? V OUT
Hz
Figure 3. LTC3538 Recommended PCB Layout
The loop gain is typically rolled off before the RHP zero
Closing the Feedback Loop
The LTC3538 incorporates voltage mode PWM control.
The control to output gain varies with operation region
(buck, boost, buck-boost), but is usually no greater than
15. The output ?lter exhibits a double pole response, as
given by:
frequency.
A simple Type I compensation network can be incorporated
to stabilize the loop, but at a cost of reduced bandwidth and
slower transient response. To ensure proper phase margin
using Type I compensation, the loop must be crossed
over a decade before the LC double pole. Referring to
? UG =
? FILTER_POLE =
(in buck mode)
1
2 ? π ? L ? C OUT
Hz
Figure 4, the unity-gain frequency of the error ampli?er
with the Type I compensation is given by:
1
Hz
2 ? π ? R1 ? C P1
V OUT
+
1V
FB
1
R1
R2
V C
2
C P1
3538 F04
Figure 4. Error Ampli?er with Type I Compensation
3538fb
12
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