参数资料
型号: LTC3544BEUD#TRPBF
厂商: Linear Technology
文件页数: 3/18页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ QUAD 16QFN
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 4
输出电压: 0.8 V ~ 5.5 V
输入电压: 2.25 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 2.25MHz
电流 - 输出: 100mA,200mA(2),300mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 16-QFN-EP(3x3)
LTC3544B
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T A = 25°C. V IN = 3.6V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V RUN(HIGH)
V RUN(LOW)
RUNx Input High Voltage
RUNx Input Low Voltage
l
l
1.0
0.3
V
V
I LSW
SWx Leakage
V RUN = 0V, V SW = 0V or 5.5V, V IN = 5.5V
±0.1
±1
μA
I RUN
RUN Leakage Current
V IN = 5.5V
l
±0.1
±1
μA
I VFB
V FBx Leakage Current
80
nA
t SS
V UVLO
Soft-Start Period
Undervoltage Lockout
V FB = 7.5% to 92.5% Full Scale
l
650
875
1.9
1200
2.25
μs
V
Individual Regulator Characteristics
Regulator SW300 – 300mA
I PK
I S300
R PFET
R NFET
Peak Switch Current Limit
Input DC Bias Current–Reg SW300 Only
Active Mode (Pulse Skip)
R DS(ON) of P-Channel FET (Note 7)
R DS(ON) of N-Channel FET (Note 7)
V FB < V FBREG , Duty Cycle < 35%
V FB = 0.7V, I LOAD = 0A, 2.25MHz
I SW = 100mA
I SW = –100mA
400
600
320
0.55
0.50
800
mA
μA
Ω
Ω
Regulator SW200A – 200mA
I PK
I S200
R PFET
R NFET
Peak Switch Current Limit
Input DC Bias Current–Reg SW200A Only
Active Mode (Pulse Skip)
R DS(ON) of P-Channel FET (Note 7)
R DS(ON) of N-Channel FET (Note 7)
V FB < V FBREG , Duty Cycle < 35%
V FB = 0.7V, I LOAD = 0A, 2.25MHz
I SW = 100mA
I SW = –100mA
300
400
320
0.65
0.60
500
mA
μA
Ω
Ω
Regulator SW200B – 200mA
I PK
I S200
R PFET
R NFET
Peak Switch Current Limit
Input DC Bias Current–Reg SW200B Only
Active Mode (Pulse Skip)
R DS(ON) of P-Channel FET (Note 7)
R DS(ON) of N-Channel FET (Note 7)
V FB < V FBREG , Duty Cycle < 35%
V FB = 0.7V, I LOAD = 0A, 2.25MHz
I SW = 100mA
I SW = –100mA
300
400
320
0.65
0.60
500
mA
μA
Ω
Ω
Regulator SW100 – 100mA
I PK
I S100
R PFET
R NFET
Peak Switch Current Limit
Input DC Bias Current–Reg SW100B Only
Active Mode (Pulse Skip)
R DS(ON) of P-Channel FET (Note 7)
R DS(ON) of N-Channel FET (Note 7)
V FB < V FBREG , Duty Cycle < 35%
V FB = 0.7V, I LOAD = 0A, 2.25MHz
I SW = 100mA
I SW = –100mA
200
300
320
0.80
0.75
400
mA
μA
Ω
Ω
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3544BE is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: T J is calculated from the ambient temperature T A and power
dissipation P D according to the following formula:
T J = T A + (P D )(68°C/W).
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: The LTC3544B is tested in a proprietary test mode that connects
V FB to the output of the error amplifier.
Note 6: Load regulation is inferred by measuring the regulation loop gain.
Note 7: The QFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
Note 8: Guaranteed by long-term current density limitations.
3544bfb
 
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