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参数资料
| 型号： | LTC3549EDCB#TR |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 0.6 A SWITCHING REGULATOR, 2700 kHz SWITCHING FREQ-MAX, PDSO6 |
| 封装： | 2 X 3 MM, 0.75 MM HEIGHT, PLASTIC, MO-229, DFN-6 |
| 文件页数： | 3/16页 |
| 文件大小： | 352K |
| 代理商： | LTC3549EDCB#TR |
LTC3549
11
3549f
LOAD CURRENT (mA)
0.1000
POWER
LOSS
(W)
1.0000
0.0100
0.0010
0.1
10
100
1000
3549 F02
0.0001
1
2.5V
3.6V
4.2V
VIN BURST
2.5V
3.6V
4.2V
VIN PULSE SKIP VOUT = 1.8V
Efciency Considerations
The efciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efciency and which change would produce
the most improvement. Efciency can be expressed as:
Efciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses in LTC3549 circuits: VIN quiescent current and
I2R losses. The VIN quiescent current loss dominates
the efciency loss at very low load currents whereas the
I2R loss dominates the efciency loss at medium to high
load currents. In a typical efciency plot, the efciency
curve at very low load currents can be misleading since
the actual power lost is of no consequence, as illustrated
in Figure 2.
1. The VIN quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge, dQ, moves
from VIN to ground. The resulting dQ/dt is the current out
of VIN that is typically larger than the DC bias current. In
continuous mode, IGATECHG = f(QT + QB) where QT and
QB are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to VIN and thus their effects will be more
pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In
continuous mode, the average output current owing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)
(1 – DC)
The RDS(ON)forboththetopandbottomMOSFETscanbe
obtained from the Typical Performance Characteristics.
Thus, to obtain I2R losses, simply add RSW to RL and
multiply the result by the square of the average output
current.
Other losses including CIN and COUT ESR dissipative los-
ses and inductor core losses generally account for less
than 2% total additional loss.
APPLICATIO S I FOR ATIO
WU
U
Figure 2. Power Loss vs Load Current
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