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参数资料
| 型号： | LTC3552EDHC-1#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC CHARGER BATT LI-ION 16-DFN |
| 标准包装： | 2,500 |
| 功能： | 充电管理 |
| 电池化学： | 锂离子（Li-Ion） |
| 电源电压： | 4.25 V ~ 8 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-WFDFN 裸露焊盘 |
| 供应商设备封装： | 16-DFN（5x3） |
| 包装： | 带卷 (TR) |
LTC3552-1
APPLICATIO S I FOR ATIO
the input capacitor is merely required to supply high
frequency bypassing, since the impedance to the supply
is very low. A 10μF ceramic capacitor is usually enough
for these conditions.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V OUT immediately shifts by an amount
equal to Δ I LOAD ? ESR, where ESR is the effective series
resistance of C OUT . Δ I LOAD also begins to charge or dis-
charge C OUT , generating a feedback error signal used by the
regulator to return V OUT to its steady-state value. During
this recovery time, V OUT can be monitored for overshoot
or ringing that would indicate a stability problem.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. A feedforward
capacitor, C FF , is added externally to improve the high
frequency response. Capacitor C FF provides phase lead by
creating a high frequency zero with R1, which improves the
phase margin. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
In some applications, a more severe transient can be caused
by switching loads with large (>1μF) input capacitors. The
discharged load input capacitors are effectively put in par-
allel with C OUT , causing a rapid drop in V OUT . No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap ? controller is designed
speci?cally for this purpose and usually incorporates cur-
rent limiting, short-circuit protection, and soft-start.
Ef?ciency Considerations
The ef?ciency of a switching regulator is equal to the
output power divided by the input power times 100%. It
is often useful to analyze individual losses to determine
what is limiting the ef?ciency and which change would
produce the most improvement. Percent ef?ciency can
be expressed as:
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3552-1 circuits: 1) V CC quiescent current, 2)
switching losses, 3) I 2 R losses, 4) other losses.
1) The V CC current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET dri-
ver and control currents. V CC current results in a small
(<0.1%) loss that increases with V CC , even at no load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from V CC to ground. The resulting dQ/dt is a current
out of V CC that is typically much larger than the DC bias
current. In continuous mode, I GATECHG = f O (Q T + Q B ),
where Q T and Q B are the gate charges of the internal
top and bottom MOSFET switches. The gate charge
losses are proportional to V CC and thus their effects
will be more pronounced at higher supply voltages.
3) I 2 R losses are calculated from the DC resistances
of the internal switches, R SW , and external inductor,
R L . In continuous mode, the average output current
?ows through inductor L, but is “chopped” between
the internal top and bottom switches. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R DS(ON) and the duty cycle
(D) as follows:
R SW = (R DS(ON)TOP )(D) + (R DS(ON)BOT )(1 – D)
The R DS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I 2 R losses:
I 2 R losses = I OUT2 (R SW + R L )
4) Other “hidden” losses such as copper trace and internal
battery resistances can account for additional ef?ciency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that C IN has adequate
% Ef?ciency = 100% – (L1 + L2 + L3 + ...)
Hot Swap is a trademark of Linear Technology Corporation.
35521fa
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