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参数资料
| 型号： | LTC3554EPD#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 0.6 A BATTERY CHARGE CONTROLLER, 2590 kHz SWITCHING FREQ-MAX, PQCC20 |
| 封装： | 3 X 3 MM, LEAD FREE, PLASTIC, UTQFN-20 |
| 文件页数： | 24/36页 |
| 文件大小： | 418K |
| 代理商： | LTC3554EPD#PBF |
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LTC3554/LTC3554-2
30
35542fb
Holding ON low through the one second power-down
period will not cause a power-up event at end of the one
second period. The ON pin must be brought high following
the power-down event and then go low again to establish
a valid power-up event.
UVLO Minimum Off-Time Timing (Low Battery)
Figure 11 assumes the battery is either missing or at a
voltage below the VOUT UVLO threshold, and the applica-
tion is running via external power (VBUS). A glitch on the
external supply causes VOUT to drop below the VOUT UVLO
threshold temporarily. This VOUT UVLO condition causes
the pushbutton circuitry to transition from the PON state
to the PDN2 state. Upon entering the PDN2 state PGOOD
will go low and the bucks power down together.
InthetypicalcasewherethePWR_ON1andPWR_ON2pins
are driven by logic powered by the bucks, the PWR_ON1
and PWR_ON2 pins would also go low, as depicted in
Figure 11. If the external supply recovers after entering
the PDN2 state such that VOUT is no longer in UVLO, then
the LTC3554 will transition back into the PUP2 state once
the PDN2 one second delay is complete. Following the
state diagram, the transition from PDN2 to PUP2 in this
case actually occurs via a brief visit to the POFF state,
during which the state machine immediately recognizes
that valid external power is available and transitions into
the PUP2 state. Entering the PUP2 state will cause the
bucks to sequence up as described previously in the
power-up sections.
Not depicted here, but in the case where the PWR_ON
pins are driven by a supply other than the bucks, and
are able to remain high while both bucks are off in the
PDN2 state, then as per the state diagram in Figure 6,
once the one second PDN2 delay is over, the pushbutton
circuitry enters the POFF state. Provided at least one
PWR_ON pin is high, and VOUT is no longer in UVLO, the
pushbutton circuitry will transition directly into the PON
state, enabling the buck(s) corresponding to the asserted
PWR_ON pin(s).
Note: If VOUTdropstoolow(belowabout1.9V)theLTC3554
will see this as a POR condition and will enter the PDN1
rather than the PDN2 state. One second later the part
will transition to the HR state. Under these conditions an
explicit power up event (such as a pushbutton press) may
be required to bring the LTC3554 out of hard reset.
Hard Reset Timing
HARD RESET provides an ultralow power-down state for
shipping or long term storage as well as a way to power
down the application in case of a software lockup. In the
case of software lockup, the user can hold the pushbut-
ton (ON low) for 5 seconds (14 seconds for LTC3554-2)
and a hard reset event (HRST) will occur, placing the
pushbutton circuitry in the power-down (PDN1) state. At
this point the bucks will be shut down and PGOOD will
go low. Following a one second power-down period the
pushbutton circuitry will enter the hard reset state (HR).
OPERATION
BAT
VBUS
ON (PB)
PBSTAT
BUCK1
BUCK2
PGOOD
PWR_ON1
PWR_ON2
STATE
PON
PUP2
PDN2
3554 TD05
5s
1s, BUCK1 POWERS UP
BUCK2 POWERS UP
230ms
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Figure 11. UVLO Minimum Off-Time Timing
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