参数资料
| 型号： | LTC3565IMSE#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 14/22页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 10MSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 最高 4MHz |
| 电流 - 输出： | 1.25A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-MSOP 裸露焊盘 |
LTC3565
APPLICATIONS INFORMATION
Checking Transient Response
The OPTI-LOOP ? compensation allows the transient re-
sponse to be optimized for a wide range of loads and output
capacitors. The availability of the ITH pin not only allows
optimization of the control loop behavior but also provides
a DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling time at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.
The ITH external components shown in the circuit on page 1
of this data sheet will provide an adequate starting point for
most applications. The series R-C filter sets the dominant
pole-zero loop compensation. The values can be modified
slightly (from 0.5 to 2 times their suggested values) to
optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1μs to 10μs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop.
Switching regulators take several cycles to respond to
a step in load current. When a load step occurs, V OUT
immediately shifts by an amount equal to Δ I LOAD ? ESR,
where ESR is the effective series resistance of C OUT .
Δ I LOAD also begins to charge or discharge C OUT generat-
ing a feedback error signal used by the regulator to return
V OUT to its steady-state value. During this recovery time,
V OUT can be monitored for overshoot or ringing that would
indicate a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C.
If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, a feedforward capacitor
C F can be added to improve the high frequency response,
as shown in Figure 2. Capacitor C F provides phase lead by
creating a high frequency zero with R2 which improves
the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
V IN
C6
+
C IN
R6
R5
C ITH
C8
R C
C C
SV IN PV IN
LTC3565
RUN
SYNC/MODE
ITH
GND
PGOOD
SW
V FB
RT
3565 F04
L1
D1
OPTIONAL
R1
R T
PGOOD
C F
R2
+
C OUT
C5
V OUT
Figure 2. LTC3565 General Schematic
3565fc
14
For more information www.linear.com/LTC3565
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