参数资料
| 型号： | LTC3565IMSE#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 17/22页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 10MSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 5 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 最高 4MHz |
| 电流 - 输出： | 1.25A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽）裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-MSOP 裸露焊盘 |
LTC3565
APPLICATIONS INFORMATION
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2μA with the 0.6V feedback voltage makes R1~300k. A close
standard 1% resistor value is 294k then R2 is 931k.
The compensation should be optimized for these compo-
nents by examining the load step response but a good place
to start for the LTC3565 is with a 12.1kΩ and 680pF filter.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.
The PGOOD pin is a common drain output and requires a pull-
up resistor. A 100k resistor is used for adequate speed.
The circuit on page 1 of this data sheet shows the complete
schematic for this design example.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3565. These items are also illustrated graphically
in the layout diagram of Figure 4. Check the following in
your layout:
1. Does the capacitor C IN connect to the power V IN (Pin 6)
and power GND (Pin 5) as close as possible? This capacitor
provides the AC current to the internal power MOSFETs
and their drivers.
2. Are the C OUT and L1 closely connected? The (–) plate of
C OUT returns current to PGND and the (–) plate of C IN .
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C OUT and a ground line. The
feedback signal V FB should be routed away from noisy
components and traces, such as the SW line (Pin 4), and
its trace should be minimized.
4. Keep sensitive components away from the SW pin. The
input capacitor C IN , the compensation capacitor C C and
C ITH and all the resistors R1, R2, R T , and R C should be
routed away from the SW trace and the inductor L1. The
SW pin pad should be kept as small as possible.
5. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small signal
components returning to the GND pin at one point.
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. These copper areas should be connected to
one of the input supply rails: PV IN , SV IN or GND.
C C
C ITH
V OUT
C OUT
R T
L1
1
2
3
4
5
RT
RUN LTC3565
SYNC/MODE
SW
GND
ITH
V FB
PGOOD
SV IN
PV IN
R C
10
9
8
7
6
R1
R5
R2
C4
3565 F06
V IN
C IN
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 4. LTC3565 Layout Diagram (See Board Layout Checklist)
3565fc
For more information www.linear.com/LTC3565
17
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