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参数资料
| 型号： | LTC3568IDD#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 4 A SWITCHING REGULATOR, 4000 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封装： | 3 X 3 MM, LEAD FREE, PLASTIC, MO-229WEED-2, DFN-10 |
| 文件页数： | 15/18页 |
| 文件大小： | 300K |
| 代理商： | LTC3568IDD#PBF |
LTC3568
3568fa
pin FuncTions
SHDN/RT (Pin 1): Combination Shutdown and Timing
Resistor Pin. The oscillator frequency is programmed by
connecting a resistor from this pin to ground. Forcing
this pin to SVIN causes the device to be shut down. In
shutdown all functions are disabled.
SYNC/MODE(Pin2): Combination Mode Selection and
Oscillator Synchronization Pin. This pin controls the op-
eration of the device. When tied to SVIN or SGND, Burst
Mode operation or pulse skipping mode is selected,
respectively. If this pin is held at half of SVIN, the forced
continuous mode is selected. The oscillation frequency
can be syncronized to an external oscillator applied to
this pin. When synchronized to an external clock pulse
skip mode is selected.
SGND (Pin 3): The Signal Ground Pin. All small signal
componentsandcompensationcomponentsshouldbecon-
nected to this ground (see Board Layout Considerations).
SW(Pin4): The Switch Node Connection to the Inductor.
This pin swings from PVIN to PGND.
PGND(Pin5): Main Power Ground Pin. Connect to the
(–) terminal of COUT, and (–) terminal of CIN.
PVIN(Pin6): Main Supply Pin. Must be closely decoupled
to PGND.
SVIN(Pin7): The Signal Power Pin. All active circuitry
is powered from this pin. Must be closely decoupled to
SGND. SVIN must be greater than or equal to PVIN.
PGOOD(Pin8): The Power Good Pin. This common drain
logic output is pulled to SGND when the output voltage is
not within ±7.5% of regulation.
VFB(Pin9): Receives the feedback voltage from the ex-
ternal resistive divider across the output. Nominal voltage
for this pin is 0.8V.
ITH(Pin10): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 1.5V.
GND (Exposed Pad Pin 11): Thermal Ground. Con-
nect to SGND and solder to the PCB for rated thermal
performance.
block DiagraM
–
+
8
9
–
+
–
+
0.74V
0.8V
ERROR
AMPLIFIER
VB
BURST
COMPARATOR
HYSTERESIS = 80mV
BCLAMP
NMOS
COMPARATOR
PMOS CURRENT
COMPARATOR
REVERSE
COMPARATOR
0.86V
5
SW
4
PGOOD
10
ITH
VFB
1
SHDN/RT
2
SYNC/MODE
3568 BD
6
PVIN
3
SGND
7
SVIN
SLOPE
COMPENSATION
VOLTAGE
REFERENCE
OSCILLATOR
LOGIC
ITH
LIMIT
–
+
–
+
–
PGND
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