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| 型号： | LTC3605EUF#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 15/22页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 5A 24QFN |
| 标准包装： | 91 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 14.9 V |
| 输入电压： | 4 V ~ 15 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 24-QFN（4x4） |
| 产品目录页面： | 1335 (CN2011-ZH PDF) |
LTC3605
OPERATION
measure the junction temperature directly is to use the
internal junction diode on one of the pins (PGOOD) to
measure its diode voltage change based on ambient
temperature change. First remove any external passive
component on the PGOOD pin, then pull out 100μA from
the PGOOD pin to turn on its internal junction diode
and bias the PGOOD pin to a negative voltage. With no
output current load, measure the PGOOD voltage at an
ambient temperature of 25°C, 75°C and 125°C to estab-
lish a slope relationship between the delta voltage on
PGOOD and delta ambient temperature. Once this slope
is established, then the junction temperature rise can be
measured as a function of power loss in the package with
corresponding output load current. Keep in mind that
doing so will violate absolute maximum voltage ratings
on the PGOOD pin, however, with the limited current, no
damage will result.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3605 (refer to Figure 3). Check the following in
your layout:
1. Do the capacitors C IN connect to the power PV IN and
power PGND as close as possible? These capacitors
provide the AC current to the internal power MOSFETs
and their drivers.
2. Are C OUT and L1 closely connected? The (–) plate of C OUT
returns current to PGND and the (–) plate of C IN .
3. The resistive divider, R1 and R2, must be connected
between the (+) plate of C OUT and a ground line termi-
nated near SGND. The feedback signal V FB should be
routed away from noisy components and traces, such
as the SW line, and its trace should be minimized. Keep
R1 and R2 close to the IC.
4. Solder the Exposed Pad (Pin 25) on the bottom of the
package to the PGND plane. Connect this PGND plane
to other layers with thermal vias to help dissipate heat
from the LTC3605.
5. Keep sensitive components away from the SW pin. The
R T resistor, the compensation capacitor C C and C ITH and
all the resistors R1, R3 and R C , and the INTV CC bypass
capacitor, should be placed away from the SW trace and
the inductor L1. Also, the SW pin pad should be kept
as small as possible.
6. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small-
signal components returning to the SGND pin which is
then connected to the PGND pin at the negative terminal
of the output capacitor, C OUT .
Flood all unused areas on all layers with copper, which
reduces the temperature rise of power components. These
copper areas should be connected to PGND.
C IN
L1
GND
V IN
V OUT
V IN
V OUT
C OUT
GND
Figure 3a. Sample PCB Layout—Topside
Figure 3b. Sample PCB Layout—Bottom Side
3605fc
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