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参数资料
| 型号： | LTC3615EUF#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING REGULATOR, PQCC24 |
| 封装： | 4 X 4 MM, LEAD FREE, PLASTIC, MO-220WGGD, QFN-24 |
| 文件页数： | 17/32页 |
| 文件大小： | 585K |
| 代理商： | LTC3615EUF#PBF |
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LTC3615/LTC3615-1
24
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DDR Application
The LTC3615 can be used in DDR memory power supply
applications by tying the SRLIM pin to SVIN. In DDR
mode, the maximum slew rate is selected. The output can
both source and sink current. Current sinking is typically
limited to 1.5A, for 1MHz frequency and 1μH inductance,
but can be lower at higher frequencies and low output
voltages. If higher ripple current can be tolerated, smaller
inductor values can increase the sink current limit. See
the Typical Performance Characteristics curves for more
information. In addition, in DDR mode, lower external
reference voltages and tracking output voltages between
channels are possible. See the Output Voltage Tracking
Input section.
Single, Low Ripple 6A Output Application
The LT3615 can generate a single, low ripple 6A output if
the outputs of the two switching regulators are tied together
and share a single output capacitor (see Figure 15 on back
of data sheet). In order to evenly share the current between
the two regulators, it is needed to connect pins FB1 to
FB2, ITH1 to ITH2 and to select forced continuous mode
at the MODE pin. To achieve lowest ripple, 90°, or better,
180°, antiphase is selected by connecting the PHASE pin
to midrail or SVIN. There are several advantages to this
2-phase buck regulator. Ripple currents at the input and
output are reduced, reducing voltage ripple and allowing
the use of smaller, less expensive capacitors. Although
two inductors are required, each will be smaller than the
inductor required for a single-phase regulator. This may
be important when there are tight height restrictions on
the circuit.
Efciency Considerations
The efciency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efciency and which change would produce
the most improvement. Efciency can be expressed as:
Efciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
APPLICATIONS INFORMATION
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: VIN quiescent current and I2R losses. The VIN
quiescent current loss dominates the efciency loss at
very low load currents whereas the I2R loss dominates
the efciency loss at medium to high load currents. In a
typical efciency plot, the efciency curve at very low load
currents can be misleading since the actual power lost is
of little consequence.
1. The VIN quiescent current is due to two components: the
DC bias current as given in the Electrical Characteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current
out of VIN due to gate charge, and it is typically larger
than the DC bias current. Both the DC bias and gate
charge losses are proportional to VIN, thus, their effects
will be more pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In
continuous mode the average output current owing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC), as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. To obtain I2R losses, simply add RSW to RL and
multiply the result by the square of the average output
current.
Other losses, including CINandCOUTESRdissipativelosses
and inductor core losses, generally account for less than
2% of the total loss.
Thermal Considerations
In most applications, the LTC3615 does not dissipate much
heat due to its high efciency. However, in applications
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| LTC3615EFE#PBF | SWITCHING REGULATOR, PDSO24 |
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相关代理商/技术参数 |
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| LTC3615HFE#PBF | 制造商:Linear Technology 功能描述:IC REG BUCK SYNC ADJ 3A 24TSSOP |
| LTC3615HFE#TRPBF | 制造商:Linear Technology 功能描述:IC REG BUCK SYNC ADJ 3A 24TSSOP |
| LTC3615HFE-1#PBF | 制造商:Linear Technology 功能描述:IC REG BUCK SYNC ADJ 3A 24TSSOP |
| LTC3615HFE-1#TRPBF | 制造商:Linear Technology 功能描述:IC REG BUCK SYNC ADJ 3A 24TSSOP |
| LTC3615HUF#PBF | 制造商:Linear Technology 功能描述:IC REG BUCK SYNC ADJ 3A 24TSSOP |
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