参数资料
型号: LTC3615EUF#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: SWITCHING REGULATOR, PQCC24
封装: 4 X 4 MM, LEAD FREE, PLASTIC, MO-220WGGD, QFN-24
文件页数: 7/32页
文件大小: 585K
代理商: LTC3615EUF#PBF
LTC3615/LTC3615-1
15
3615fa
Operating Frequency
Selection of the operating frequency is a trade-off between
efciency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efciency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency of the LTC3615 is determined by
an external resistor that is connected between pin RT/SYNC
and ground. The value of the resistor sets the ramp current
that is used to charge and discharge an internal timing
capacitor within the oscillator and can be calculated by
using the following equation:
R
Hz
f
T
OSC
=
41011
Ω
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3615 imposes a minimum
limit on the operating duty cycle. The minimum on-time
APPLICATIONS INFORMATION
is typically 60ns, therefore, the minimum duty cycle is
equal to 60ns 100% fOSC(Hz)
Tying the RT/SYNC pin to SVIN sets the default internal
operating frequency to 2.25MHz ±20%.
Frequency Synchronization
The LTC3615’s internal oscillator can be synchronized to
an external frequency by applying a square wave clock
signal to the RT/SYNC pin. During synchronization, the
top MOSFET turn-on of channel 1 is locked to the rising
edge of the external frequency source. The synchronization
frequency range is 400kHz to 4MHz. The internal slope
compensation is automatically adapted to the external
clock frequency.
In the signal path from the RT/SYNC clock input to the
SW output, the LTC3615 is processing the external clock
frequency through an internal PLL.
After detecting an external clock on the rst rising edge
of RT/SYNC the PLL starts up with the internal default of
2.25MHz. The internal PLL then requires a certain number
Figure 3. Soft-Start and Compensation for Channel 1 Externally Programmed,
Soft-Start and Compensation for Channel 2 Internally Programmed
(2 ) SW1
FB1
MODE
LTC3615
3615 F03
SGND
PGND
RUN1
TRACK/SS1
RT, 200k
ITH1
PHASE
RUN2
TRACK/SS2
PGOOD2
ITH2
PGOOD1
RT /SYNC
SRLIM
VIN
3.3V
SVIN (2 ) PVIN1 (2 ) PVIN2
1μF
47μF
0.47μH
47μF
VOUT1
1.8V/3A
R1
422k
R2
29.4k
R3
178k
RSS
4.7M
CSS
10nF
RC
15k
CC
1000pF
(2 ) SW2
FB2
0.47μH
47μF
VOUT2
2.5V/3A
R5
665k
R4
210k
10pF
RSRLIM
40.2k
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