参数资料
型号: LTC3703IGN-5#PBF
厂商: Linear Technology
文件页数: 19/32页
文件大小: 0K
描述: IC REG CTRLR BST PWM VM 16-SSOP
标准包装: 100
PWM 型: 电压模式
输出数: 1
频率 - 最大: 330kHz
占空比: 96%
电源电压: 4.1 V ~ 15 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
包装: 管件
LTC3703-5
APPLICATIO S I FOR ATIO
C2
IN
R2
C1
–6dB/OCT
A V
0
GAIN
PHASE
–12dB/OCT
FREQ
–90
R1
FB
R B
V REF
+
OUT
0
GAIN
–6dB/OCT
FREQ
–90
–6dB/OCT
–180
–270
PHASE
–180
–270
–360
37035 F10
Figure 10. Transfer Function of Buck Modulator
feedback amplifier, on the other hand, gives us a handle
with which to adjust the AC response. The goal is to have
180 ° phase shift at DC (so the loop regulates) and some-
thing less than 360 ° phase shift at the point that the loop
gain falls to 0dB. The simplest strategy is to set up the
feedback amplifier as an inverting integrator, with the 0dB
frequency lower than the LC pole (Figure 11). This “Type
1” configuration is stable but transient response is less
than exceptional if the LC pole is at a low frequency.
–360
37035 F12
Figure 12. Type 2 Schematic and Transfer Function
for an extended frequency range. LTC3703-5 circuits
using conventional switching grade electrolytic output
capacitors can often get acceptable phase margin with
Type 2 compensation.
“Type 3” loops (Figure 13) use two poles and two zeros to
obtain a 180 ° phase boost in the middle of the frequency
band. A properly designed Type 3 circuit can maintain
acceptable loop stability even when low output capacitor
ESR causes the LC section to approach 180 ° phase shift
well above the initial LC roll-off. As with a Type 2 circuit,
IN
R1
C1
GAIN
the loop should cross through 0dB in the middle of the
phase bump to maximize phase margin. Many LTC3703-5
FB
–6dB/OCT
circuits using low ESR tantalum or OS-CON output capaci-
R B
V REF
+
OUT
0
PHASE
FREQ
–90
–180
–270
tors need Type 3 compensation to obtain acceptable phase
margin with a high bandwidth feedback loop.
IN
C2
–360
37035 F11
C3
R2
C1
Figure 11. Type 1 Schematic and Transfer Function
R1
R3
FB
–6dB/OCT
GAIN
+6dB/OCT
–6dB/OCT
Figure 12 shows an improved “Type 2” circuit that uses an
additional pole-zero pair to temporarily remove 90 ° of
phase shift. This allows the loop to remain stable with 90 °
more phase shift in the LC section, provided the loop
R B
V REF
+
OUT
0
PHASE
FREQ
–90
–180
–270
–360
reaches 0dB gain near the center of the phase “bump.”
Type 2 loops work well in systems where the ESR zero in
the LC roll-off happens close to the LC pole, limiting the
total phase shift due to the LC. The additional phase
compensation in the feedback amplifier allows the 0dB
point to be at or above the LC pole frequency, improving
loop bandwidth substantially over a simple Type 1 loop. It
has limited ability to compensate for LC combinations
where low capacitor ESR keeps the phase shift near 180 °
37035 F13
Figure 13. Type 3 Schematic and Transfer Function
Feedback Component Selection
Selecting the R and C values for a typical Type 2 or Type 3
loop is a nontrivial task. The applications shown in this
data sheet show typical values, optimized for the power
components shown. They should give acceptable perfor-
mance with similar power components, but can be way off
37035fa
19
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