参数资料
型号: LTC3722IGN-2#PBF
厂商: Linear Technology
文件页数: 17/28页
文件大小: 0K
描述: IC REG CTRLR DIV ISO PWM 24SSOP
标准包装: 55
PWM 型: 电压模式,全桥
输出数: 1
频率 - 最大: 1MHz
占空比: 98.5%
电源电压: 3.8 V ~ 10.3 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
包装: 管件
LTC3722-1/LTC3722-2
OPERATION
C T =
is designed so that the positive voltage square wave is
produced while the output inductor is freewheeling. An
advantage of this technique over the previous is that it
does not require a separate filter inductor and since the
voltage is derived from the well regulated output voltage, it
is also well controlled. One disadvantage is that this wind-
ing will require the same safety isolation that is required
for the main transformer. Another disadvantage is that a
much larger V CC filter capacitor is needed, since it does
not generate a voltage as the output is first starting up,
or during short-circuit conditions.
Programming the LTC3722-1/LTC3722-2 Oscillator
The high accuracy LTC3722-1/LTC3722-2 oscillator circuit
provides flexibility to program the switching frequency,
slope compensation, and synchronization with minimal
external components. The LTC3722-1/LTC3722-2 oscillator
circuitry produces a 2.2V peak-to-peak amplitude ramp
waveform on C T and a narrow pulse on SYNC that can be
used to synchronize other PWM chips. Typical maximum
duty cycles of 98.5% are obtained at 300kHz and 96% at
1MHz. A compensating slope current is derived from the
oscillator ramp waveform and sourced out of CS.
The desired amount of slope compensation is selected
with single external resistor. A capacitor to GND on C T
programs the switching frequency. The C T ramp discharge
current is internally set to a high value (>10mA). The dedi -
cated SYNC I/O pin easily achieves synchronization. The
LTC3722-1/LTC3722-2 can be set up to either synchronize
other PWM chips or be synchronized by another chip or
external clock source. The 1.8V SYNC threshold allows the
LTC3722-1/LTC3722-2 to be synchronized directly from
all standard 3V and 5V logic families.
Design Procedure:
1. Choose C T for the desired oscillator frequency. The
switching frequency selected must be consistent with
the power magnetics and output power level. In general,
increasing the switching frequency will decrease the
maximum achievable output power, due to limitations
of maximum duty cycle imposed by transformer core
reset and ZVS. Remember that the tranformer fre-
quency is one-half that of the oscillator.
1
(13.4 k ? f OSC )
Example: Desired f OSC = 330kHz
C T = 1/(13.4k ? f OSC ) = 226pF, choose closest standard
value of 220pF. A 5% or better tolerance multilayer NPO
or X7R ceramic capacitor is recommended for best
performance.
2. The LTC3722-1/LTC3722-2 can either synchronize other
PWMs, or be synchronized to an external frequency
source or PWM chip (see Figure 8 for details).
SYNC
C T OF SLAVE(S) IS
1.25 C T OF MASTER.
LTC3722
C T
C T
MASTER
SYNC
1k
5.1k 1k
?
? 5.1k
?
UP TO
5 SLAVES
SYNC
5.1k
SYNC
LTC3722
LTC3722
SLAVES
C T
C T
372212 F08a
C T
C T
EXTERNAL
FREQUENCY
SOURCE
AMPLITUDE > 1.8V
100ns < PW < 0.4/ ?
1k
5.1k
LTC3722
C T
C T
372212 F08b
Figure 8a. SYNC Output (Master Mode)
Figure 8b. SYNC Input from an External Source
372212fb
For more information www.linear.com/LTC3722
17
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