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参数资料
| 型号： | LTC3734EUH#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 14/28页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR DC/DC 1PH HI EFF 32QFN |
| 标准包装： | 73 |
| 应用： | 控制器，Intel 移动式 CPU |
| 输入电压： | 4 V ~ 30 V |
| 输出数： | 1 |
| 输出电压： | 0.7 V ~ 1.71 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
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LTC3734
APPLICATIONS INFORMATION
P SWTOP = V IN2 ?
? f ? C RSS ? R DR ?
I OUT
? V DR – V TH(MIN)
V TH(MIN) ?
I RMS ? I OUT(MAX)
V OUT V IN
V IN
V OUT
MOSFETthresholdvoltage,thenonlinearityofcurrentris-
ing/falling characteristic and the Miller Effect. Given the
data in a typical power MOSFET data sheet, the switch-
ing losses of the top and bottom MOSFETs can only be
estimated as follows:
(7)
2
? 1 1 ?
? + ?
P SWBOT ≈ 0 (8)
where R DR is the effective driver resistance (of approxi-
mately 2Ω), V DR is the driving voltage (= PV CC ) and V TH(MIN)
is the minimum gate threshold voltage of the MOSFET.
Please notice that the switching loss of the bottom MOSFET
is effectively negligible because the current conduction of
the antiparalleling diode. This effect is often referred as
zero-voltage-transition (ZVT). Similarly when the LTC3734
converter works under fully synchronous mode at light
load, the reverse inductor current can also go through
the body diode of the top MOSFET and make the turn-on
loss to be negligible. However, equations 7 and 8 have to
be used in calculating the worst-case power loss, which
happens at highest load level.
The selection criteria of power MOSFETs start with the
stress check:
V IN < BV DSS
I MAX < I D(MAX)
and
P CONTOP + P SWTOP < top MOSFET maximum power
dissipation specification
P CONBOT + P SWBOT < bottom MOSFET maximum power
dissipation specification
The maximum power dissipation allowed for each MOSFET
depends heavily on MOSFET manufacturing and pack-
aging, PCB layout and power supply cooling method.
Maximum power dissipation data are usually specified
in MOSFET data sheets under different PCB mounting
conditions.
The next step of selecting power MOSFETs is to minimize
the overall power loss:
P OVL = P TOP + P BOT
= (P CONTOP + P DRTOP + P SWTOP ) + (P CONBOT +
P DRBOT + P SWBOT )
For typical mobile CPU applications where the ratio between
input and output voltages is higher than 2:1, the bottom
MOSFET conducts load current most of the time while
the main losses of the top MOSFET are for switching and
driving. Therefore a low R DS(ON) part (or multiple parts in
parallel) would minimize the conduction loss of the bottom
MOSFET while a higher R DS(ON) but lower Q G and C RSS
part would be desirable for the top MOSFET.
The Schottky diode, D1 in Figure 1, conducts during the
dead-time between the conduction of the top and bottom
MOSFETs. This helps reduce the current flowing through
the body diode of the bottom MOSFET. A body diode usu-
ally has a forward conduction voltage higher than that of a
Schottky and is thus detrimental to efficiency. The charge
storage and reverse recovery of a body diode also cause
high frequency rings at the switching nodes (the conjunc-
tion nodes between the top and bottom MOSFETs), which
are again not desired for efficiency or EMI. Some power
MOSFET manufacturers integrate a Schottky diode with a
power MOSFET, eliminating the need to parallel an external
Schottky. These integrated Schottky-MOSFETs, however,
have smaller MOSFET die sizes than conventional parts
and are thus not suitable for high current applications.
C IN and C OUT Selection
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V OUT /
V IN . A low ESR input capacitor sized for the maximum
RMS current must be used. The RMS input ripple current
is estimated to be:
? 1
This formula has a maximum at V IN = 2V OUT , where
I RMS = I OUT(MAX) /2
3734fa
14
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