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参数资料
| 型号： | LTC3734EUH#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR DC/DC 1PH HI EFF 32QFN |
| 标准包装： | 73 |
| 应用： | 控制器，Intel 移动式 CPU |
| 输入电压： | 4 V ~ 30 V |
| 输出数： | 1 |
| 输出电压： | 0.7 V ~ 1.71 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
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LTC3734
APPLICATIONS INFORMATION
RUN/SS
1.5V
By using different value R6 resistors, V DPRSLPVR can be
programmed.
V OUT
V BOOT
90% V BOOT
V VID
(The digital input threshold voltage is 1.8V for STP_CPUB,
DPRSLPVR and MCH_PG inputs.)
t BOOT
TIME
STP% = –
? 100%
INTERNALPG
(OUTPUT OF
INTERNAL
POWER GOOD
COMPARATOR)
MCH_PG
COMPOSITE PG
(=(INTERNAL PG)
AND (MCH_PG))
MD
VALID
INVALID
VID BITS
3734 F04
Figure 4. Start-Up Timing Diagram
Output Voltage Set in Deep Sleep and Deeper Sleep
States (Refer to the Functional Diagram)
The output voltage can be offset by the STP_CPUB signal.
When STP_CPUB becomes low, the output voltage will be
a certain percentage lower than that set by the VID bits in
Table 1. This state is defined to be the deep sleep state.
Referring to the Functional Diagram, we can calculate the
STP_CPUB offset to be:
R3
R3 + R4
Power Good Masking
The PGOOD output monitors V OUT . When V OUT is not
within ±10% of the set point, PGOOD is pulled low with
an internal MOSFET. When V OUT is within the regulation
window, PGOOD is of high impedance. PGOOD should be
pulled up by an external resistor.
During VID changes, deep sleep and deeper sleep transi-
tions, the output voltage can initially be out of the ±10%
window of the newly set regulation point. To avoid nui-
sance indications from PGOOD, a timer masks PGOOD for
110μs. If output is still out of regulation after this blanking
time, PGOOD goes low. Any overvoltage or undervoltage
condition is also masked for 110μs before it is reported
by PGOOD.
The masking circuitry also adaptively tracks VID and state
changes. If a new change in VID or state happens before
the 110μs masking timer expires, the timer resets and
starts a fresh count of 110μs. This prevents the system
from rebooting under frequent output voltage transitions.
Refer to Figure 5 for the PGOOD timing diagram.
During start up, PGOOD is actively pulled low until the
RUN/SS pin voltage reaches its arming voltage, which
VID BITS
R2 ? ( R3 + R6 R4 )
( ) ? ( )
V DPRSLPVR = 0.6V ?
ByusingdifferentR4resistors,STP_CPUBoffsetcanbe
programmed.
The output voltage could also be set by external resistors
R4 and R6 when DPRSLPVR input is high. This state is
defined to be the deeper sleep state. The output voltage
is set to V DPRSLPVR , regardless of the VID setting:
R6 R4 R1 + R2
V OUT
INTERNAL PG
(OUTPUT OF
INTERNAL
POWER GOOD
COMPARATOR)
PGOOD
MASKING
PGOOD
110μs
TIME
110μs
3734 F05
where R6||R4 is the parallel combination of R4 and R6.
Figure 5. PGOOD Timing Diagram
3734fa
17
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