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| 型号： | LTC3734EUH#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/28页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR DC/DC 1PH HI EFF 32QFN |
| 标准包装： | 73 |
| 应用： | 控制器，Intel 移动式 CPU |
| 输入电压： | 4 V ~ 30 V |
| 输出数： | 1 |
| 输出电压： | 0.7 V ~ 1.71 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
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LTC3734
APPLICATIONS INFORMATION
VID Output Voltage Programming
After 27μs ~ 71μs t BOOT delay, the output voltage of the
regulator is digitally programmed as defined in Table 1
using the VID0 to VID5 logic input pins. The VID logic
inputs program a precision, 0.25% internal feedback re-
sistive divider. The LTC3734 has an output voltage range
of 0.700V to 1.708V in 16mV steps.
By pulling the RUN/SS pin below 1V the LTC3734 is put
into low current shutdown (I Q < 100μA). The RUN/SS pin
can be driven directly from logic as shown in Figure 3.
Diode D1 in Figure 3 reduces the start delay but allows
C SS to ramp up slowly providing the soft-start function.
The RUN/SS pin has an internal 6V zener clamp (see
Functional Diagram).
Refering to the Functional Diagram, there is a resistor,
R VID , from V FB to ground. The value of R VID is controlled
by the six VID input pins. Another internal resistor, 5.33k
(R ATTEN ), completes the resistive divider. The output voltage
is thus set by the ratio of (R VID + 5.33k) to R VID .
3.3V OR 5V
D1
PV CC
RUN/SS
R SS *
C SS
RUN/SS
C SS
3734 F03
= ( 1s/ μ F ) C SS
t DELAY =
C
R2 ? ( R3 + R5 )
R5 ? ( )
V BOOT = 0.6V ?
t BOOT = 15
Each VID digital pin is a high impedance input. There-
fore they must be actively pulled high or pulled low. The
logic low threshold of the VID pins is 0.3V; the logic high
threshold is 0.7V.
Soft-Start/Run Function
The RUN/SS pin provides three functions: 1) run/shutdown,
2) soft-start and 3) an optional short-circuit latchoff timer.
Soft-start reduces the input power source’s surge currents
by gradually increasing the controller’s current limit. The
latchoff timer prevents very short, extreme load transients
from tripping the overcurrent latch. A small pull-up cur-
rent (>5μA) supplied to the RUN/SS pin will prevent the
overcurrent latch from operating. The following paragraph
describes how the functions operate.
An internal 1.5μA current source charges up the soft-start
capacitor, C SS . When the voltage on RUN/SS reaches 1.5V,
the controller is permitted to start operating. As the volt-
age on RUN/SS increases from 1.5V to 3.0V, the internal
current limit is increased from 25mV/R SENSE to 72mV/
R SENSE . The output current thus ramps up slowly, elimi-
nating the starting surge current required from the input
power supply. If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:
1.5V
1.5 μ A SS
The time for the output current to ramp up is then:
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
Figure 3. RUN/SS Pin Interfacing
Start-Up Sequence (Refer to the Functional Diagram)
After soft-start, the output voltage of the regulator settles
at a voltage level equal to V BOOT .
R1 + R2
By using different R5 resistors, V BOOT can be programmed.
After the output voltage enters the ±10% regulation window
centered at V BOOT , the internal power good comparator
issues a logic high signal. Refer to the timing diagram in
Figure 4. This signal then enters a logic AND gate, with
MCH_PG being the other input, and the output of the gate
is PG shown in Figure 4. This composite PG signal is then
delayed by t BOOT amount of time and then becomes MD.
As soon as MD is asserted, the output voltage changes
from V BOOT to V VID , a voltage level totally controlled by
the six VID bits. In the LTC3734, the time t BOOT is set to
be 15 switching cycles:
1
f S
If f S is set at 210kHz, t BOOT = 71μs
If f S is set at 550kHz, t BOOT = 27μs
t IRAMP =
3V ? 1.5V
1.5 μ A
C SS = ( 1s/ μ F ) C SS
3734fa
16
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