参数资料
型号: LTC3773EUHF#PBF
厂商: Linear Technology
文件页数: 20/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 38-QFN
标准包装: 52
系列: PolyPhase®
PWM 型: 电流模式
输出数: 3
频率 - 最大: 630kHz
占空比: 98.5%
电源电压: 3.3 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 38-WFQFN 裸露焊盘
包装: 管件
LTC3773
APPLICATIONS INFORMATION
SENSE + /SENSE – Pins
The common mode input range of the current compara-
tor sense pins is from 0V to (1.1)V CC . Continuous linear
operation is guaranteed throughout this range allowing
output voltage setting from 0.6V to 7.7V, depending upon
the voltage applied to V CC . A differential NPN input stage
is biased with internal resistors from an internal 2.4V
source as shown in Figure 1. This requires that current
either be sourced or sunk from the SENSE pins depending
on the regulator output voltage. If the output voltage is
below 2.4V, current will ?ow out of both SENSE pins to
the main output. The output can be easily preloaded by
the V OUT resistive divider to compensate for the current
comparator’s negative input bias current. The maximum
current ?owing out of each pair of SENSE pins is:
small external capacitor larger than 100pF at the SDB pin
reduces the slew rate at the node, permitting the internal
circuit to settle before actual conversion begins.
LTC3773 can be easily con?gured to produce a sequential
power up/down supply. By adding an external capacitor
at the SDB pin; or by controlling the SDB input voltage,
channel 1 will be powered up ?rst, followed by channel
2 and sequentially channel 3. The channel turn on time
delay is determined by the SDB capacitor value. Figure 4
shows the sequential power up/down con?guration and
its waveform. The capacitor at the TRACK pins control
the individual channel power up slew rate.
LTC3773
TRACK1
TRACK2
I SENSE + + I SENSE – = 2 ?
2.4V – V OUT
60k
RAMP
SOURCE
C SLEW
SDB1
SDB2
SDB3
TRACK3
Since V FB is servoed to the 0.6V reference voltage, we
1M Ω
C SS
can choose R1 in Figure 1 to have a maximum value to
absorb this current.
POWER
DOWN
0V TO 2V
10k
R1 (MAX) = 30k
0.6V
2.4V – V OUT
for V OUT < 2.4V
SDB
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 30k. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the
sense currents; however, R1 is still bounded by the V FB
feedback current.
1V/DIV
2.5V V OUT1 1V/DIV
1.8V V OUT2 1V/DIV
1.2V V OUT3 1V/DIV
Power Up from Shutdown
0.1s/DIV
3773 F04
If the SDB1, SDB2 and SDB3 pins are forced below 0.4V,
the IC enters low current shutdown mode. Under this
condition, most of the internal circuit blocks, including
the reference, are disabled. The supply current drops to a
typical value of 20μA. Disconnecting the external applied
voltage source allows an internal 0.5μA current source to
pull up the SDBn pin. Once the voltage at any of the SDB
pins is above the shutdown threshold, the reference and
the internal biasing circuit wake up. When the voltage at
the SDBn pin goes above its power-up threshold, its driver
starts to toggle. The power-up thresholds for channels 1, 2
and 3 are set at 1.2V, 1.8V and 2.4V respectively. Adding a
Figure 4. Sequential Power Up/Down
Soft-Start/Tracking
When the voltage on the TRACK pin is less than the
internal 0.6V reference, the LTC3773 regulates the V FB
voltage to the TRACK pin voltage instead of 0.6V. After
the soft-start/tracking cycle, the TRACK pin voltage must
be higher than 0.8V; otherwise, the tracking circuit intro-
duces offset in the error ampli?er and the switcher output
will be regulated to a slightly lower potential. If tracking is
not required, a soft-start capacitor should be connected
to the TRACK pin to regulate the output startup slew rate.
3773fb
20
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