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| 型号： | LTC3773EUHF#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 22/32页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 38-QFN |
| 标准包装： | 52 |
| 系列： | PolyPhase® |
| PWM 型： | 电流模式 |
| 输出数： | 3 |
| 频率 - 最大： | 630kHz |
| 占空比： | 98.5% |
| 电源电压： | 3.3 V ~ 36 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 包装： | 管件 |
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LTC3773
APPLICATIONS INFORMATION
add an extra tracking resistive divider. When the tracking
resistive divider input is grounded, the pull-up current ?ow-
ing through the network could produce a small unwanted
offset at the TRACK pin, forcing the controller to create
an unwanted low voltage supply at the regulator output.
To compensate for this error, the LTC3773 introduces a
30mV offset in the tracking circuit, which disables the
driver until the potential at the TRACK pin is above 30mV.
The magnitude of this offset diminishes as the potential
at the TRACK pin approaches 100mV, allowing accurate
tracking after startup.
Fault Conditions: Current Limit and Current Foldback
The LTC3773 current comparator has a maximum sense
voltage of 75mV resulting in a maximum MOSFET cur-
rent of 75mV/R SENSE . The maximum value of current
limit generally occurs with the largest V IN at the highest
ambient temperature, conditions that cause the highest
power dissipation in the top MOSFET.
The LTC3773 includes current foldback to help further
limit load current when the output is shorted to ground.
If the potential at the TRACK pin is above 0.54V and the
V FB voltage falls below 70% of its nominal level, then the
maximum sense voltage is progressively lowered from
75mV to 15mV. Under short-circuit conditions with very
low duty cycles, the LTC3773 will begin cycle skipping in
order to limit the short-circuit current. In this situation
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time, t ON(MIN) ,
of the LTC3773 (less than 200ns), the input voltage and
stays at 75mV and the regulator current limit remains at
its rated value. This feature allows the LTC3773 to power
the core and I/O of low voltage FPGAs.
When power is ?rst applied to an FPGA, the device can
draw current several times its normal operating current.
This power-on surge current is due to the programmable
nature of FPGAs. When the FPGA powers up, before ini-
tialization, the RAM cells are brie?y in a random state. This
results in contention at the interconnect and signi?cant
power dissipation. The duration of the power-on surge
current is typically quite brief but can cause problems
for power supply designs. LTC3773 views currents that
are outside the normal operation range as possible short-
circuits. Disabling the current foldback at startup allows
the regulator to provides a higher surge current to meet
the FPGA’s requirement. Nevertheless, when calculating
the current sense resistor value for FPGA power supply
applications, the computed output current value must be
higher than the power-on surge current to allow a proper
startup.
Fault Conditions: Overvoltage Protection
A comparator monitors the output for overvoltage
conditions. The comparator (OV) detects overvoltage
faults greater than 3.75% above the nominal output volt-
age. When this condition is sensed, the top MOSFET is
turned off and the bottom MOSFET is turned on until the
overvoltage condition is cleared. The bottom MOSFET
remains on continuously for as long as the OV condition
persists. If V OUT returns to a safe level, normal operation
automatically resumes.
inductor value:
I L(SC) = t ON(MIN)
V IN
L
Note that under extreme power-up conditions, e.g. with
high input voltage, a small inductor and a small soft-start
capacitor, once the OV comparator trips, the output volt-
age might continue to charge above the rated value until
The resulting short-circuit current is:
the energy in the inductor is depleted. The peak of the
I SC =
15mV
R SENSE
1
2
I L(SC)
overshoot might be higher than the rated voltage of the
output capacitors.
Disable Current Foldback at Start-Up
At start-up, if the potential at the TRACK pin is lower than
0.54V, the LTC3773 current comparator threshold voltage
Phase-Locked Loop and Frequency Synchronization
The LTC3773 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the external N channel
3773fb
22
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