参数资料
型号: LTC3778EF#TR
厂商: Linear Technology
文件页数: 18/24页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 20TSSOP
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
电源电压: 4 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
包装: 带卷 (TR)
其它名称: LTC3778EFTR
LTC3778
APPLICATIO S I FOR ATIO
C SS
0.1 μ F
R3
11k
R4
39k
1
2
R PG
100k 3
LTC3778
RUN/SS BOOST
VON TG
PGOOD SW
20
19
18
D B
CMDSH-3
C B
0.22 μ F
M1
Si4884
L1, 1.8 μ H
C IN
10 μ F
35V
× 3
V IN
5V TO 28V
V OUT
2.5V
10A
C C1
500pF
R C
20k
C C2
4
5
6
V RNG
I TH
FCB
SENSE +
SENSE –
PGND
17
16
15
M2
Si4874
D1
B340A
+
C OUT1-2
180 μ F
4V
× 2
C OUT3
22 μ F
6.3V
X7R
100pF
7
SGND
BG
14
C ON , 0.01 μ F
R1
8
I ON
DRV CC
13
C VCC
4.7 μ F
12.7k
R2
40.2k
R ON
400k
9
10
V FB
EXTV CC
INTV CC
V IN
12
11
R F
1 ?
C F
0.1 μ F
3778 F07
C IN : UNITED CHEMICON THCR60EIHI06ZT
C OUT1-2 : CORNELL DUBILIER ESRE181E04B
L1: SUMIDA CEP125-1R8MC-H
Figure 7. Design Example: 2.5V/10A at 250kHz
(
)
± 20 A ? ? 0 . 015 ? = ± 50 mV = 100 mV
Active Voltage Positioning
Active voltage positioning (also termed load “deregula-
tion” or droop) describes a technique where the output
voltage varies with load in a controlled manner. It is useful
in applications where rapid load steps are the main cause
of error in the output voltage. By positioning the output
voltage at or above the regulation point at zero load, and
below the regulation point at full load, one can use more
of the error budget for the load step. This allows one to
reduce the number of output capacitors by relaxing the
ESR requirement.
For example, in a 20A application, six 0.015 ? capacitors
are required in parallel to keep the output voltage within a
100mV tolerance:
? 1 ?
? 6 ?
Using active voltage positioning, the same specification
can be met with only three capacitors. In this case, the load
step will cause an output voltage change of:
By positioning the output voltage at the regulation point at
no load, it will drop 100mV below the regulation point after
the load step. However, when the load disappears or the
output is stepped from 20A to 0A, the 100mV is recovered.
This way, a total of 100mV change is observed on V OUT in
all conditions, whereas a total of ± 100mV or 200mV is
seen on V OUT without voltage positioning while using only
three output capacitors.
Implementing active voltage positioning requires setting a
precise gain between the sensed current and the output
voltage. Because of the variability of MOSFET on-resis-
tance, it is prudent to use a sense resistor with active
voltage positioning. In order to minimize power lost in this
resistor, a low value of 0.002 ? is chosen. The nominal
sense voltage will now be:
V SNS(NOM) = (0.002 ? )(20A) = 40mV
To maintain a reasonable current limit, the voltage on the
V RNG pin is reduced to 0.5V by connecting it to a resistor
divider from INTV CC , corresponding to a 50mV nominal
sense voltage.
Next, the gain of the LTC3778 error amplifier must be
( ) (
)
= 20 A ? ? 0 . 015 ? = 100 mV
? V OUT ( STEP )
18
? 1 ?
? 3 ?
determined. The change in I TH voltage for a corresponding
change in the output current is:
3778f
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