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参数资料
| 型号： | LTC3785EUF-1#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM VM 24-QFN |
| 标准包装： | 91 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 1MHz |
| 占空比： | 99% |
| 电源电压： | 2.7 V ~ 10 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 包装： | 管件 |
LTC3785-1
OPERATION
of the voltage loop, resulting in a lower output voltage
to regulate the input current. This fault condition causes
the RUN/SS capacitor to begin discharging. The level of
the discharge current depends on how much the current
exceeds the programmed threshold. Figure 3 is a simpli-
?ed diagram of the current sense and fault circuitry. If the
current limit fault duration is long enough to discharge the
RUN/SS capacitor below 1.225V, the fault latch is set and
will cycle the RUN/SS capacitor 16 times (1μA charging
and 1μA discharging of the RUN/SS capacitor) to create an
off time of 32 times the soft-start time before the outputs
are allowed to switch to restart the output voltage. If the
current limit fault level exceeds 150% of the programmed
I LIMIT level at any time, the I MAX comparator is tripped and
output switches B and D are turned on to discharge the
inductor current for the remainder of the cycle.
To have the power converter latch off on a fault, a pull-up
current between 4μA and 7μA on the RUN/SS pin will allow
the RUN/SS capacitor to discharge during an extended
fault, but will prevent cycling of the fault which will cause the
converter to stay off. One method to implement this is by
THERMAL SD
placing a diode (anode tied to V OUT ) and a resistor from V OUT
to the RUN/SS pin. The current sourced into RUN/SS will be
V OUT – 0.7 divided by the resistor value. To ignore all faults
source greater than 40μA into the RUN/SS pin (At 1.225V on
the RUN/SS pin). Since the maximum fault current is limited,
this will prevent any discharging of the RUN/SS capacitor,
the soft-start capacitor will need to be sized accordingly to
accommodate the extra charging current at start-up.
During an output short-circuit or if V OUT is less than 1.8V, the
current limit folds back to 50% of the programmed level.
REVERSE CURRENT LIMIT
The LTC3785-1 can be programmed to provide full class D
operation or allowed to source and sink current equal to
the current limit set value. This is achieved by asserting a
high level on the CCM pin. To minimize the reverse output
current, the CCM pin should be driven low or strapped to
ground. During this mode only, –15mV typical is allowed
across output switch D and is sensed with the I SVOUT and
I SSW2 pins.
+
1.225V
0.7V
+
–
S FAULT
S LOGIC
RUN
I LIMIT COMP
g m = 1/20k
g m
–
V = 60k/R ILSET
(15k/R ILSET WHEN V OUT < 1.8V)
I SVIN
22
TG1 20
V IN
A
C SS
1
RUN/SS
2.2V
1μA
TURN
SWITCHES
B AND D ON
I MAX COMP
+
–
+
X10
–
SAMPLED
SW1 19
I SSW1
18
10μA MAX
CCM = HIGH = 6k/R ILSET CCM
CCM = LOW = 15mV
4
1/3 ? I LIM(OUT)
2μA
I LIM(OUT)
30μA MAX
V = 90k/R ILSET
BG1 17
6
B
L1
V OUT
R1
C P1
3
2
FB
V C
1.225V
+
–
ERROR AMP
SWITCH D
OFF
REVERSE
CURRENT LIMIT
–
+
I SVOUT
10
TG2 12
SW2 13
D
V OUT
C OUT
R2
R ILSET
5
I LSET
I LIMIT
SET
I LIM COMP
I MAX COMP
SAMPLED
I SSW2
14
BG2 15
C
37851 F03
Figure 3. Block Diagram of Current Limit Fault Circuitry
37851fa
11
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