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| 型号： | LTC3785EUF-1#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 17/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BST PWM VM 24-QFN |
| 标准包装： | 91 |
| PWM 型： | 电压模式 |
| 输出数： | 2 |
| 频率 - 最大： | 1MHz |
| 占空比： | 99% |
| 电源电压： | 2.7 V ~ 10 V |
| 降压： | 是 |
| 升压： | 是 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 包装： | 管件 |
LTC3785-1
APPLICATIONS INFORMATION
PC BOARD LAYOUT CHECKLIST
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
? The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
? Place C IN , switch A, switch B and D1 in one compact
area. Place C OUT , switch C, switch D and D2 in one
compact area.
? Use immediate vias to connect the components (includ-
ing the LTC3785-1’s GND/PGND pin) to the ground plane.
Use several large vias for each power component.
? Use planes for V IN and V OUT to maintain good voltage
?ltering and to keep power losses low.
? Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to any DC net
(V IN or GND). When laying out the printed circuit board,
the following checklist should be used to ensure proper
operation of the LTC3785-1.
? Segregate the signal and power grounds. All small-signal
components should return to the GND pin at one point.
The sources of switch B and switch C should also con-
nect to one point at the GND of the IC.
? Place switch B and switch C as close to the controller
as possible, keeping the PGND, BG and SW traces
short.
? Keep the high dV/dT SW1, SW2, V BST1 , V BST2 , TG1 and
TG2 nodes away from sensitive small-signal nodes.
? The path formed by switch A, switch B, D1 and the C IN
capacitor should have short leads and PC trace lengths.
The path formed by switch C, switch D, D2 and the
C OUT capacitor also should have short leads and PC
trace lengths.
? The output capacitor (–) terminals should be connected
as close as possible to the (–) terminals of the input
capacitor.
? Connect the V CC decoupling capacitor C VCC closely to
the V CC and PGND pins.
? Connect the top driver boost capacitor C A closely to
the V BST1 and SW1 pins. Connect the top driver boost
capacitor C B closely to the V BST2 and SW2 pins.
? Connect the input capacitors C IN and output capaci-
tors C OUT close to the power MOSFETs. These capaci-
tors carry the MOSFET AC current in boost and buck
mode.
? Connect FB and V SENSE pin resistive dividers to the (+)
terminals of C OUT and signal ground. If a small V SENSE
decoupling capacitor is used, it should be as close as
possible to the LTC3785-1 GND pin.
? Route I SVIN and I SSW1 leads together with minimum
PC trace spacing. Ensure accurate current sensing
with Kelvin connections across MOSFET A or sense
resistor.
? Route I SVOUT and I SSW2 leads together with minimum
PC trace spacing. Ensure accurate current sensing
with Kelvin connections across MOSFET D or sense
resistor.
? Connect the feedback network close to IC, between the
V C and FB pins.
37851fa
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