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参数资料
| 型号： | LTC3822EGN-1#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 15/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 16-SSOP |
| 标准包装： | 100 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 850kHz |
| 占空比： | 99% |
| 电源电压： | 2.75 V ~ 4.5 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 产品目录页面： | 1336 (CN2011-ZH PDF) |
LTC3822-1
APPLICATIONS INFORMATION
over temperature and process variations, to be between
250kHz and 750kHz. A simpli?ed block diagram is shown in
Figure 6.
If the external clock frequency is greater than the internal
oscillator’s frequency, f OSC , then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f OSC , current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
The loop ?lter components, C LP and R LP , smooth out
the current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. These ?lter
components determine how fast the loop acquires lock.
Typically R LP = 10k and C LP is 2200pF to 0.01μF.
Typically, the external clock (on SYNC/MODE pin) input
high level is 1.6V, while the input low level is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2. The States of the PLLLPF Pin
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the ?lter capacitor C LP holds the voltage.
PLLLPF PIN
0V
Floating
V IN
RC Loop Filter
SYNC/MODE PIN
DC Voltage
DC Voltage
DC Voltage
Clock Signal
FREQUENCY
300kHz
550kHz
750kHz
Phase-Locked
to External Clock
1200
Using a Sense Resistor (GN Only)
1000
800
600
400
200
A sense resistor R SENSE can be connected between V IN and
SENSE – to sense the output load current. In this case, the
drain of the topside N-channel MOSFET is connected to
SENSE – pin and the source is connected to the SW pin of
the LTC3822-1. Therefore the current comparator moni-
tors the voltage developed across R SENSE , not the V DS of
the top MOSFET. The output current that the LTC3822-1
? V SENSE ( MAX ) I RIPPLE
R SENSE
0
0.2
0.7 1.2 1.7
PLLLPF PIN VOLTAGE (V)
2.2
38221 F05
can provide in this case is given by:
I OUT ( MAX ) = –
2
Figure 5. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
Setting ripple current as 40% of I OUT(MAX) and using
Figure 1 to choose SF, the value of R SENSE is:
2.4V
R LP
C LP
R SENSE =
5
6
? SF ?
? V SENSE ( MAX )
I OUT ( MAX )
EXTERNAL
OSCILLATOR
SYNC/
MODE
DIGITAL
PHASE/
FREQUENCY
DETECTOR
PLLLPF
OSCILLATOR
Variation in the resistance of a sense resistor is much
smaller than the variation in on-resistance of an external
MOSFET. Therefore the load current is well controlled
with a sense resistor. However the sense resistor causes
I 2 R losses in addition to those of the MOSFET. Therefore,
using a sense resistor lowers the ef?ciency of LTC3822-1,
38221 F06
especially at high load current.
Figure 6. Phase-Locked Loop Block Diagram
38221f
15
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| LTC3823EGN#TRPBF | 功能描述:IC REG CTRLR BUCK PWM CM 28-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:96% 电源电压:4 V ~ 36 V 降压:无 升压:是 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 125°C 封装/外壳:24-WQFN 裸露焊盘 包装:带卷 (TR) |
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