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| 型号： | LTC3830ES#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 16-SOIC |
| 标准包装： | 50 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 250kHz |
| 占空比： | 95% |
| 电源电压： | 3 V ~ 8 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 产品目录页面： | 1336 (CN2011-ZH PDF) |
LTC3830/LTC3830-1
APPLICATIO S I FOR ATIO
Table 3 shows the suggested compensation component
values for 5V to 3.3V applications based on 470 μ F Sanyo
POSCAP 4TPB470M output capacitors.
Table 3. Recommended Compensation Network for 5V to 3.3V
Applications Using Multiple Paralleled 470 μ F Sanyo POSCAP
4TPB470M Output Capacitors
L1 ( μ H) C OUT ( μ F) R C (k ? ) C C (nF) C1 (pF)
1.2 1410 6.8 4.7 33
1.2 2820 15 2.2 33
1.2 4700 22 2.2 33
2.4 1410 18 10 33
LAYOUT CONSIDERATIONS
When laying out the printed circuit board, use the follow-
ing checklist to ensure proper operation of the LTC3830.
These items are also illustrated graphically in the layout
diagram of Figure 11. The thicker lines show the high
current paths. Note that at 10A current levels or above,
current density in the PC board itself is a serious concern.
Traces carrying high current should be as wide as pos-
sible. For example, a PCB fabricated with 2oz copper
requires a minimum trace width of 0.15" to carry 10A.
2.4
2.4
4.7
4.7
4.7
2820
4700
1410
2820
4700
43
62
43
91
150
2.2
2.2
10
33
10
33
10
10
10
10
1. In general, layout should begin with the location of the
power devices. Be sure to orient the power circuitry so that
a clean power flow path is achieved. Conductor widths
should be maximized and lengths minimized. After you are
satisfied with the power path, the control circuitry should
Table 4 shows the suggested compensation component
values for 5V to 3.3V applications based on 1500 μ F Sanyo
MV-WX output capacitors.
Table 4. Recommended Compensation Network for 5V to 3.3V
Applications Using Multiple Paralleled 1500 μ F Sanyo MV-WX
Output Capacitors
be laid out. It is much easier to find routes for the relatively
small traces in the control circuits than it is to find
circuitous routes for high current paths.
2. The GND and PGND pins should be shorted directly at
the LTC3830. This helps to minimize internal ground dis-
turbances in the LTC3830 and prevent differences in ground
L1 ( μ H)
1.2
1.2
1.2
2.4
2.4
2.4
4.7
4.7
4.7
C OUT ( μ F)
4500
6000
9000
4500
6000
9000
4500
6000
9000
R C (k ? )
22
30
39
51
62
82
100
150
200
C C (nF)
1.5
1
0.47
1
1
0.47
3.3
0.47
0.47
C1 (pF)
120
82
56
56
33
27
15
15
15
potential from disrupting internal circuit operation. This
connection should then tie into the ground plane at a single
point, preferably at a fairly quiet point in the circuit such as
close to the output capacitors. This is not always practical,
however, due to physical constraints. Another reasonably
good point to make this connection is between the output
capacitors and the source connection of the bottom
MOSFET Q2. Do not tie this single point ground in the trace
run between the Q2 source and the input capacitor ground,
as this area of the ground plane will be very noisy.
3830fa
18
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