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参数资料
| 型号： | LTC3850IUF#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 23/38页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 28-QFN |
| 产品培训模块： | LTC3850 Dual Output DC/DC Switching Regulator Controller |
| 标准包装： | 2,500 |
| 系列： | PolyPhase® |
| PWM 型： | 电流模式 |
| 输出数： | 2 |
| 频率 - 最大： | 860kHz |
| 占空比： | 97.2% |
| 电源电压： | 4 V ~ 30 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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LTC3850/LTC3850-1
APPLICATIONS INFORMATION
FREQ/PLLFLTR PIN VOLTAGE (V)
t ON(MIN) < OUT
VCO
900
800
700
600
500
400
300
200
100
0
0 0.5 1 1.5 2 2.5
38501 F10
Figure 10. Relationship Between Oscillator
Frequency and Voltage at the FREQ/PLLFLTR Pin
2.4V
R LP
C LP
FREQ/
PLLFLTR
MODE/
PLLIN DIGITAL
EXTERNAL PHASE/
OSCILLATOR FREQUENCY
DETECTOR
38501 F11
Figure 11. Phase-Locked Loop Block Diagram
tinuously from the phase detector output, pulling up the
FREQ/PLLFLTR pin. When the external clock frequency
is less than f OSC , current is sunk continuously, pulling
down the FREQ/PLLFLTR pin. If the external and internal
frequencies are the same but exhibit a phase difference,
the current sources turn on for an amount of time corre-
sponding to the phase difference. The voltage on the FREQ/
PLLFLTR pin is adjusted until the phase and frequency of
the internal and external oscillators are identical. At the
stable operating point, the phase detector output is high
impedance and the filter capacitor C LP holds the voltage.
The loop filter components, C LP and R LP , smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components C LP and R LP determine how fast the loop
acquires lock. Typically R LP = 10k and C LP is 2200pF to
0.01μF.
Typically, the external clock (on MODE/PLLIN pin)
input high threshold is 1.6V, while the input low thres-
hold is 1V.
Minimum On-Time Considerations
Minimum on-time t ON(MIN) is the smallest time duration
that the LTC3850 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
V
V IN (f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3850 is approximately
90ns, with reasonably good PCB layout, minimum 30%
inductor current ripple and at least 10mV – 15mV ripple
on the current sense signal. The minimum on-time can be
affected by PCB switching noise in the voltage and current
loop. As the peak sense voltage decreases the minimum
on-time gradually increases to 130ns. This is of particular
concern in forced continuous applications with low ripple
current at light loads. If the duty cycle drops below the
minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
38501fc
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相关代理商/技术参数 |
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| LTC3851AEGN#PBF | 功能描述:IC REG CTRLR BUCK PWM CM 16-SSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 特色产品:LM3753/54 Scalable 2-Phase Synchronous Buck Controllers 标准包装:1 系列:PowerWise® PWM 型:电压模式 输出数:1 频率 - 最大:1MHz 占空比:81% 电源电压:4.5 V ~ 18 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-5°C ~ 125°C 封装/外壳:32-WFQFN 裸露焊盘 包装:Digi-Reel® 产品目录页面:1303 (CN2011-ZH PDF) 其它名称:LM3754SQDKR |
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