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| 型号： | LTC3879EUD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 12/28页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM CM 16-QFN |
| 标准包装： | 121 |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 2MHz |
| 占空比： | 90% |
| 电源电压： | 4 V ~ 38 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-WFQFN 裸露焊盘 |
| 包装： | 管件 |
| 产品目录页面： | 1336 (CN2011-ZH PDF) |
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LTC3879
APPLICATIONS INFORMATION
The resulting power dissipation in the MOSFETs at maxi-
V IN
? ( C MILLER )
+ V I N 2 ?
? ?
mum output current are:
P TOP = D TOP ? I OUT ( MAX ) 2 ? ρ τ ( TOP ) ? R DS ( ON )( MAX )
? I OUT(MAX ) ?
2
V GS
MILLER EFFECT
a b
Q IN
C MILLER = (Q B – Q A )/V DS
V
+
V GS
–
+ V DS
–
3879 F02
+
V MILLER ? OSC
? V INTVC C – V MILLER
C MILLER =
( )
t ON =
? DR TGHIGH DR TGLOW ?
? ? f
P BOT = D BO T ? I OUT ( MAX ) 2 ? ρ τ ( BOT ) ? R DS ( ON )( MAX )
DR TGHIGH is pull-up driver resistance and DR TGLOW is the
TG driver pull-down resistance. V MILLER is the Miller ef-
fect V GS voltage and is taken graphically from the power
MOSFET data sheet.
MOSFET input capacitance is a combination of several
components but can be taken from the typical “gate charge”
curve included on the most data sheets (Figure 2). The
curve is generated by forcing a constant input current
into the gate of a common source, current source, loaded
stage and then plotting the gate versus time. The initial
slope is the effect of the gate-to-source and gate-to-drain
capacitance. The ?at portion of the curve is the result of the
Miller multiplication effect of the drain-to-gate capacitance
as the drain drops the voltage across the current source
load. The upper sloping line is due to the drain-to-gate
accumulation capacitance and the gate-to-source capaci-
tance. The Miller charge (the increase in coulombs on the
horizontal axis from a to b while the curve is ?at) is speci-
?ed from a given V DS drain voltage, but can be adjusted
for different V DS voltages by multiplying by the ratio of
the application V DS to the curve speci?ed V DS values. A
way to estimate the C MILLER term is to take the change in
gate charge from points a and b or the parameter Q GD on
a manufacturers data sheet and divide by the speci?ed
V DS test voltage, V DS(TEST) .
Q GD
V DS ( TEST )
Figure 2. Gate Charge Characteristic
Both MOSFETs have I 2 R power loss, and the top MOSFET
includes an additional term for transition loss, which are
highest at high input voltages. For V IN < 20V, the high cur-
rent ef?ciency generally improves with larger MOSFETs,
while for V IN > 20V, the transition losses rapidly increase
to the point that the use of a higher R DS(ON) device with
lower C MILLER actually provides higher ef?ciency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
Operating Frequency
The choice of operating frequency is a tradeoff between
ef?ciency and component size. Lowering the operating fre-
quency improves ef?ciency by reducing MOSFET switching
losses but requires larger inductance and/or capacitance
to maintain low output ripple voltage. Conversely, raising
the operating frequency degrades ef?ciency but reduces
component size.
The operating frequency of LTC3879 applications is de-
termined implicitly by the one-shot timer that controls the
on-time, t ON , of the top MOSFET switch. The on-time is
set by the current into the I ON pin according to:
0 . 7 V
10 pF
I ION
Tying a resistor R ON from V IN to the I ON pin yields an
on-time inversely proportional to V IN . For a step-down
converter, this results in pseudo ?xed frequency operation
as the input supply varies.
C MILLER is the most important selection criteria for deter-
mining the transition loss term in the top MOSFET but is
not directly speci?ed on MOSFET data sheets.
f OP =
V OUT
0 . 7 V ? R ON ( 10 pF
)
[ Hz ]
3879f
12
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