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参数资料
| 型号： | LTC4009IUF-2#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 24/28页 |
| 文件大小： | 0K |
| 描述： | IC CHARGER BATTERY MC 20-QFN |
| 标准包装： | 91 |
| 功能： | 充电管理 |
| 电池化学： | 多化学 |
| 电源电压： | 6 V ~ 28 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 供应商设备封装： | 20-QFN 裸露焊盘（4x4） |
| 包装： | 管件 |
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LTC4009
LTC4009-1/LTC4009-2
APPLICATIONS INFORMATION
PCB Layout Considerations
To prevent magnetic and electrical field radiation and
high frequency resonant problems, proper layout of the
components connected to the LTC4009 is essential. Refer
to Figure 12. For maximum efficiency, the switch node
rise and fall times should be minimized. The following
PCB design priority list will help insure proper topology.
Layout the PCB using this specific order.
1. Input capacitors should be placed as close as possible
to switching FET supply and ground connections with
the shortest copper traces possible. The switching
FETs must be on the same layer of copper as the input
capacitors. Vias should not be used to make these
connections.
2. Place the LTC4009 close to the switching FET gate
terminals, keeping the connecting traces short to
produce clean drive signals. This rule also applies to IC
supply and ground pins that connect to the switching
FET source pins. The IC can be placed on the opposite
side of the PCB from the switching FETs.
3. Place the inductor input as close as possible to the
switching FETs. Minimize the surface area of the switch
node. Make the trace width the minimum needed to
support the programmed charge current. Use no cop-
per fills or pours. Avoid running the connection on
multiple copper layers in parallel. Minimize capacitance
from the switch node to any other trace or plane.
SWITCH NODE
4. Place the charge current sense resistor immediately
adjacent to the inductor output, and orient it such
that current sense traces to the LTC4009 are not long.
These feedback traces need to be run together as a
single pair with the smallest spacing possible on any
given layer on which they are routed. Locate any filter
component on these traces next to the LTC4009, and
not at the sense resistor location.
5. Place output capacitors adjacent to the sense resistor
output and ground.
6. Output capacitor ground connections must feed into
the same copper that connects to the input capacitor
ground before connecting back to system ground.
7. Connection of switching ground to system ground,
or any internal ground plane, should be single-point.
If the system has an internal system ground plane,
a good way to do this is to cluster vias into a single
star point to make the connection.
8. Route analog ground as a trace tied back to the LTC4009
GND paddle before connecting to any other ground.
Avoid using the system ground plane. A useful CAD
technique is to make analog ground a separate ground
net and use a 0 Ω resistor to connect analog ground
to system ground.
9. A good rule of thumb for via count in a given high
current path is to use 0.5A per via. Be consistent when
applying this rule.
V IN
L1
R SENSE
V BAT
C IN
HIGH
FREQUENCY
CIRCULATING
PATH
D1
C OUT
+
BAT
GND
SWITCHING GROUND
4009 F12
ANALOG
GROUND
SYSTEM
GROUND
Figure 12. High Speed Switching Path
4009fd
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