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参数资料
| 型号： | LTC4216IMS#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/26页 |
| 文件大小： | 311K |
| 描述： | IC CNTRLR HOT SWAP 10-MSOP |
| 标准包装： | 50 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 2.3 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 管件 |
LTC4216
8
4216fa
For more information www.linear.com/LTC4216
operaTion
The LTC4216 is a Hot Swap controller residing either on a
removable circuit board or on the backplane. It monitors
the current and protects the load with an external N-channel
MOSFET and a current sensing resistor (see Figures 14
to 18). Both inrush current limiting and short-circuit protec-
tion are provided by the LTC4216. The device is powered
via the bias supply input (V
CC
) and it has a separate sense
pin, SENSEP, to monitor the load supply (V
IN
). The load
supply can extend from 0V to 6V, with a minimum bias
supply voltage of 2.3V.
When the ON pin is pulled from low to high, TIMER begins
the first timing cycle by sourcing 2礎 into C1 once these
conditions are met: bias supply voltage out of undervolt-
age lockout (> 2.12V); TIMER, SS, FILTER and GATE
pin voltages < 0.2V. When the C1 voltage rises above
the TIMER pin threshold (1.253V), TIMER pulls low and
releases both the SS and GATE pins. C2 starts to ramp
up at the SS pin, controlling the rate of GATE ramp. This
limits the rate of change of the inrush current flowing into
the output load capacitance. RESET pin goes high after
the second timing cycle when the FB pin voltage exceeds
0.6V and its hysteresis.
When the external MOSFET is fully turned on, the output
will ramp to load supply voltage if the inrush into the load
capacitance is low. However, if the inrush current exceeds
the analog current limit of 擵
ACL(TH)
/R
SENSE
, the LTC4216
will ramp the output by sourcing the limited current into
the load capacitance.
The LTC4216 provides protection against output short-
circuits or current overload through an internal electronic
circuit breaker with trip threshold of 25mV and an analog
current limit circuit. The circuit breaker response time is
set by C3 at the FILTER pin.
block DiagraM
+
+
+
+
+
+
+
+
+
+
0.2V
2.12V
0.4V
0.8V
0.6V
2礎
2.4礎
1.253V
CP1
CP6
CP7
CP5
CP4
V
CC
V
CC
V
CC
SENSEP
SENSEN
GATE
SS**
RESET
ON
FB
4216 BD
FAULT**
GND
TIMER
FILTER
NORMAL
UVLO
ECB
ACL
NOTE 1: FILTER DELAY IS SET BY FILTER PIN CAPACITOR
** ONLY AVAILABLE IN THE DE12 PACKAGE
V
CC
V
CC
CP2
CP3
1.253V
1.253V
6祍
DELAY
FAULT LATCH
RESET
DEVICE
RESET
FAULT LATCH-OFF
OUT OF UVLO
CB TRIPS
OR UVLO
GATE
ON
GATE
OFF
M4
M3
M2
M1
M5
M6
R1
M7
M9
M10
M8
Z1
D1
D2
CHARGE
PUMP
100礎
20礎
40mV
25mV
10礎
1礎
5礎
GATE ON
GATE OFF
DEVICE RESET, UVLO
OR POWER BAD
CB
TRIPS
FILTER
FUNCTION OF
OVERDRIVE
FILTER DELAY
(SEE NOTE 1)
30祍
DELAY
60礎
V
CC
LOGIC
3祍
DELAY
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