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参数资料
| 型号： | LTC4225IUFD-2#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 4/24页 |
| 文件大小： | 346K |
| 描述： | IC CONTROLLER HOT SWAP 24-QFN |
| 标准包装： | 73 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电流限制： | 可调 |
| 电源电压： | 2.9 V ~ 18 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（5x4） |
| 包装： | 管件 |
LTC4225-1/LTC4225-2
4
422512f
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25癈. V
IN
= 12V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
HGATE(UP)
External N-Channel Gate Pull-Up Current
Gate Drive On, HGATE = 0V
l
7
10
13
礎
I
HGATE(DN)
External N-Channel Gate Pull-Down
Current
Gate Drive Off, OUT = 12V ,
HGATE = OUT + 5V
l
150
300
500
礎
I
HGATE(FPD)
External N-Channel Gate Fast
Pull-Down Current
Fast Turn-Off, OUT = 12V ,
HGATE = OUT + 5V
l
100
200
300
mA
t
PHL(SENSE)
Sense Voltage (INn SENSEn)
High to HGATEn Low
V
SENSE
= 300mV , C
HGATE
= 10nF
l
0.5
1
祍
t
OFF(HGATE)
ENn High to HGATEn Low
ONn Low to HGATEn Low
INn Low to HGATEn Low
l
l
l
20
10
10
40
20
20
祍
祍
祍
t
D(HGATE)
ONn High, ENn Low to HGATEn
Turn-On Delay
l
50
100
150
ms
t
P(HGATE)
ONn to HGATEn Propagation Delay
ON = Step 0.8V to 2V
l
10
20
祍
Input/Output Pin
I
SENSE
SENSEn Input Current
SENSE = 12V
l
10
50
100
礎
V
ON(TH)
ONn Threshold Voltage
ON Rising
l
1.21
1.235
1.26
V
V
ON(HYST)
ONn Hysteresis
l
40
80
140
mV
V
ON(RESET)
ONn Fault Reset Threshold Voltage
ON Falling
l
0.55
0.6
0.63
V
I
ON(LEAK)
ONn Input Leakage Current
ON = 5V
l
0
?
礎
V
EN(TH)
ENn Threshold Voltage
EN Rising
l
1.185
1.235
1.284
V
V
EN(HYST)
ENn Hysteresis
l
40
130
200
mV
I
EN(UP)
ENn Pull-Up Current
EN = 1V
l
7
10
13
礎
V
TMR(TH)
TMRn Threshold Voltage
TMR Rising
TMR Falling
l
l
1.198
0.15
1.235
0.2
1.272
0.25
V
V
I
TMR(UP)
TMRn Pull-Up Current
TMR = 1V , In Fault Mode
l
75
100
125
礎
I
TMR(DN)
TMRn Pull-Down Current
TMR = 2V , No Faults
l
1.4
2
2.6
礎
I
TMR(RATIO)
TMRn Current Ratio I
TMR(DN)
/I
TMR(UP)
l
1.4
2
2.7
%
I
OUT
OUTn Current
OUT = 11V , IN = 12V , ON = 2V
OUT = 13V , IN = 12V , ON = 2V
l
l
50
2.2
120
4
礎
mA
V
OL
Output Low Voltage (FAULTn, PWRGDn)
I = 1mA
l
0.15
0.4
V
V
OH
Output High Voltage (FAULTn, PWRGDn)
I = 1礎
l
INTV
CC
1 INTV
CC
0.5
V
I
OH
Input Leakage Current (FAULTn, PWRGDn) V = 18V
l
0
?
礎
I
PU
Output Pull-Up Current
(FAULTn, PWRGDn)
V = 1.5V
l
7
10
13
礎
t
RST(ON)
ONn Low to FAULTn High
l
20
40
祍
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of
the device pins are negative. All voltages are referenced to GND unless
otherwise specified.
Note 3: An internal clamp limits the DGATE and CPO pins to a minimum of
10V above and a diode below IN. Driving these pins to voltages beyond the
clamp may damage the device.
Note 4: An internal clamp limits the HGATE pin to a minimum of 10V
above and a diode below OUT . Driving this pin to voltages beyond the
clamp may damage the device.
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