参数资料
型号: LTC4252-2CMS8#TRPBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 电源管理
英文描述: Negative Voltage Hot Swap Controllers; Package: MSOP; No of Pins: 8; Temperature Range: 0°C to +70°C
中文描述: 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封装: LEAD FREE, PLASTIC, MSOP-8
文件页数: 17/36页
文件大小: 336K
代理商: LTC4252-2CMS8#TRPBF
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
24
425212fc
APPLICATIONS INFORMATION
Undervoltage Timing
In Figure 11 when UV pin drops below VUVLO (time point1),
the LTC4252 shuts down with TIMER, SS and GATE all
pulling low. If current has been flowing, the SENSE pin
voltage decreases to zero as GATE collapses. When UV
recovers and clears VUVHI (time point 2), an initial timer
cycle begins followed by a GATE start-up cycle.
VIN Undervoltage Lockout Timing
The VIN undervoltage lockout comparator, UVLO, has a
similar timing behavior as the UV pin timing except it looks
for VIN < (VLKO – VLKH) to shut down and VIN > VLKO to
start. In an undervoltage lockout condition, both UV and
OV comparators are held off. When VIN exits undervoltage
lockout, the UV and OV comparators are enabled.
Undervoltage Timing with Overvoltage Glitch
In Figure 12, both UV and OV pins are connected together.
When UV clears VUVHI (time point 1), an initial timing
cycle starts. If the system bus voltage overshoots VOVHI
as shown at time point 2, TIMER discharges. At time point
3, the supply voltage recovers and drops below the VOVLO
threshold. The initial timing cycle restarts, followed by a
GATE start-up cycle.
Overvoltage Timing
During normal operation, if the OV pin exceeds VOVHI as
shown at time point 1 of Figure 13, the TIMER and PWRGD
status are unaffected. Nevertheless, SS and GATE pull down
and the load is disconnected. At time point 2, OV recovers
and drops below the VOVLO threshold. A GATE start-up
cycle begins. If the overvoltage glitch is long enough to
deplete the load capacitor, a full start-up cycle as shown
between time points 4 through 7 may occur.
Circuit Breaker Timing
In Figure 14a, the TIMER capacitor charges at 230μA if
the SENSE pin exceeds VCB but VDRN is less than 5V. If
the SENSE pin drops below VCB before TIMER reaches
UV
TIMER
GATE
SENSE
SS
DRAIN
PWRGD
5.8μA
58μA
5.8μA
58μA
UV DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
12
3 4 56
7
8 9
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB
OS
10 11
425212 F11
UV CLEARS VUVHI, CHECK OV CONDITION, GATE < VGATEL, SENSE < VCB
OS AND TIMER < VTMRL
VACL
VCB
DRN
OS
VIN – VGATEH
VDRNL
VDRNCL
CB + VOS)
ACL + VOS)
VGATEL
VTMRL
VTMRH
VUVHI
VUVLO
GATE
START-UP
INITIAL TIMING
Figure 11. Undervoltage Timing (All Waveforms Are Referenced to VEE)
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