参数资料
型号: LTC4252-2CMS8#TRPBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 电源管理
英文描述: Negative Voltage Hot Swap Controllers; Package: MSOP; No of Pins: 8; Temperature Range: 0°C to +70°C
中文描述: 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封装: LEAD FREE, PLASTIC, MSOP-8
文件页数: 22/36页
文件大小: 336K
代理商: LTC4252-2CMS8#TRPBF
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
29
425212fc
APPLICATIONS INFORMATION
current begins to decline below VACL(t). The current limit
loop shuts off and GATE releases at time point 8. At time
point9, the SENSE voltage falls below VCB and TIMER
deactivates.
Large values of CSS can cause premature circuit breaker
time out as VACL(t) may exceed the VCB potential during
the circuit breaker delay. The load capacitor is unable to
achieve full charge in one GATE start-up cycle. A more
serious side effect of large CSS values is SOA duration
may be exceeded during soft-start into a low impedance
load. A soft-start voltage below VCB will not activate the
circuit breaker TIMER.
Power Limit Circuit Breaker
Figure 19 shows the LTC4252A-1 in a power limit circuit
breaking application. The SENSE pin is modulated by the
board supply voltage, VSUPPLY. The D1 Zener voltage, VZ
is set to be the same as the low supply operating voltage,
VSUPPLY(MIN) = 43V. If the goal is to have the high supply
operating voltage, VSUPPLY(MAX) = 71V giving the same
power at VSUPPLY(MIN), then resistors R4 and R6 are
selected using the ratio:
R6
R4
=
VCB
VSUPPLY(MAX)
(16)
If R6 is 27Ω, R4 is 38.3k. The peak circuit breaker power
limit is:
POWERMAX =
VSUPPLY(MIN) +VSUPPLY(MAX)
()2
4 VSUPPLY(MIN) VSUPPLY(MAX)
POWERSUPPLY(MIN)
=1.064 POWERSUPPLY(MIN)
(17)
when
VSUPPLY = 0.5 (VSUPPLY(MIN) + VSUPPLY(MAX)) = 57V.
The peak power at the fault current limit occurs at the supply
overvoltage threshold. The fault current limited power is:
POWERFAULT =
VSUPPLY
RS
VACL –VSUPPLY –VZ
()R6
R4
(18)
TIMER
GATE
SENSE
SS
DRAIN
VTMRH
VDRNCL
VACL
VCB
VDRNL
VGS(th)
VIN – VGATEH
VTMRL
425212 F18
PWRGD
5.8μA
58μA
TIMER
GATE
SENSE
SS
DRAIN
VTMRH
VDRNCL
VCB
VACL
VDRNL
VGS(th)
VIN – VGATEH
VTMRL
PWRGD
5.8μA
58μA
12 34 567
7a
8 9
10
11
END OF INTIAL TIMING CYCLE
12 3 4 5 6
7
8 9
10
11
END OF INTIAL TIMING CYCLE
OS
CB + VOS)
ACL + VOS)
OS
CB + VOS)
ACL + VOS)
DRN
Figure 18. Soft-Start Timing (All Waveforms Are Referenced to VEE)
(18a) Without External CSS
(18b) With External CSS
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