参数资料
型号: LTC4365CTS8#TRMPBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封装: LEAD FREE, PLASTIC, MO-193, TSOT-23, 8 PIN
文件页数: 4/16页
文件大小: 369K
代理商: LTC4365CTS8#TRMPBF
LTC4365
12
4365f
The trace at VOUT, on the other hand, does not respond
to the negative voltage at VIN, demonstrating the desired
reverse supply protection. The waveforms of Figure 7 were
captured using a 40V dual N-channel MOSFET, a 10μF
ceramic output capacitor and no load current on VOUT.
Recovery Timer
The LTC4365 has a recovery delay timer that filters noise
at VIN and helps prevent chatter at VOUT. After either an OV
or UV fault has occurred, the input supply must return to
the desired operating voltage window for at least 36ms in
order to turn the external MOSFET back on as illustrated
in Figures 4 and 5.
Going out of and then back into fault in less than 36ms
will keep the MOSFET off continuously. Similarly, coming
out of shutdown (SHDN low to high) triggers an 800μs
start-up delay timer (see Figure 10).
The recovery timer is also active while the LTC4365 is
powering up. The 36ms timer starts once VIN rises above
VIN(UVLO) and VIN lies within the user selectable UV/OV
power good window. See Figure 8.
Gentle Shutdown
The SHDN input turns off the external MOSFETs in a
gentle, controlled manner. When SHDN is asserted low,
a 90μA current sink slowly begins to turn off the external
MOSFETs.
Once the voltage at the GATE pin falls below the voltage
at the VOUT pin, the current sink is throttled back and a
feedback loop takes over. This loop forces the GATE voltage
to track VOUT, thus keeping the external MOSFETs off as
VOUT decays. Note that when VOUT < 4.5V, the GATE pin
is pulled to within 400mV of ground.
Gentle gate turn off reduces load current slew rates and
mitigates voltage spikes due to parasitic inductances.
To further decrease GATE pin slew rate, place a capaci-
tor across the gate and source terminals of the external
MOSFETs. The waveforms of Figure 9 were captured using
the Si4230 dual N-channel MOSFETs, and a 2A load with
100μF output capacitor.
APPLICATIONS INFORMATION
4365 F08
GATE
MOSFET OFF
MOSFET ON
VIN
VIN(UVLO)
tRECOVERY
Figure 8. Recovery Timing During Power-On
(OV = GND, UV = SHDN = VIN)
Figure 9. Gentle Shutdown: GATE Tracks VOUT as
VOUT Decays
GATE
VOUT
tGATE(SLOW)
GATE = VOUT
tSTART
tSHDN(F)
ΔVGATE
SHDN
4365 F10
FAULT
Figure 10. Gentle Shutdown Timing
FAULT Status
The FAULT high voltage open drain output is driven low if
SHDN is asserted low, if VIN is outside the desired UV/OV
voltage window, or if VIN has not risen above VIN(UVLO).
Figures 4, 5 and 10 show the FAULT output timing.
5V/DIV
4365 F9
100μs/DIV
GATE
VOUT
SHDN
VIN = 12V
T = 25°C
GND
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