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参数资料
| 型号： | LTC691ISW#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC MPU SUPERVISRY CIRCUIT 16SOIC |
| 标准包装： | 47 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 35 ms |
| 电压 - 阀值： | 4.65V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
V CC
+
LTC691
62512
10μF
V BATT
3V
V CC
+
LTC690
LTC694
5V V CC V OUT
5V V CC V OUT
0.1μF 0.1μF
LTC695 RAM
CE OUT CS
20ns PROPAGATION DELAY GND
CE IN FROM DECODER
RESET
GND RESET
TO μP
690 F06
Figure 6. A Typical Nonvolatile CMOS RAM Application
0.1μF 10μF 0.1μF 62128
RAM
CS CS1
V BATT RESET CS2
3V GND GND
690 F07
Figure 7. Write Protect for RAM with LTC690 or LTC694
Power-Fail Warning
The LTC690 family generates a Power Failure Output ( PFO )
for early warning of failure in the microprocessor’s power
supply. This is accomplished by comparing the Power
Failure Input (PFI) with an internal 1.3V reference. PFO
goes low when the voltage at the PFI pin is less than 1.3V.
Typically PFI is driven by an external voltage divider (R1 and
R2 in Figures 8 and 9) which senses either an unregulated
DC input or a regulated 5V output. The voltage divider ratio
can be chosen such that the voltage at the PFI pin falls
below 1.3V several milliseconds before the 5V supply falls
below the maximum reset voltage threshold 4.75V. PFO is
normally used to interrupt the microprocessor to execute
shutdown procedure between PFO and RESET or RESET.
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resistor
between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower
trip points in the comparator are established as follows:
V H = 1.3V ? 1 +
+
?
R3 ?
?
V IN ≥ 7.5V
+
10μF
R1
51k
R2
10k
LT1086-5
V IN V OUT
ADJ
+
100μF
R3
300k
5V
0.1μF
R4
10k
V CC
LTC690/LTC691
LTC694/LTC695
PFO
GND
PFI
690 F08
TO μP
When PFO output is low, R3 sinks current from the sum-
ming junction at the PFI pin.
? R1 R1 ?
R2
When PFO output is high, the series combination of R3
and R4 source current into the PFI summing junction.
V L = 1.3V ? 1 +
Figure8.MonitoringUnregulatedDCSupply
with the LTC690’s Power-Fail Comparator
?
?
R1
R2
?
(5V ? 1.3V) R1 ?
1.3V (R3 + R4) ? ?
V IN V OUT
+
ADJ
10μF
LTC690/LTC691
R3
Assuming R4 << R3,V HYSTERESIS = 5V
V IN ≥ 6.5V
+
10μF
LT1086-5
5V
V CC
R1 R4 0.1μF
27k 10k
LTC694/LTC695
2.7M
PFO
PFI GND
R2
8.2k 1690 F09
TO μP
R5
3.3k
Figure 9. Monitoring Regulated DC Supply
with the LTC690’s Power-Fail Comparator
R1
R3
Example 1: The circuit in Figure 8 demonstrates the use
of the power-fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of
the supply input V IN is 100mV/ms and the total time to
execute a shutdown procedure is 8ms. Also the noise of
V IN is 200mV. With these assumptions in mind, we can
reasonably set V L = 7.5V which 1.25V greater than the sum
of maximum reset voltage threshold and the dropout volt-
age of LT1086-5 (4.75V + 1.5V) and V HYSTERESIS = 850mV.
690ff
12
For more information www.linear.com/690
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