参数资料
型号: LTC6990IS6#TRPBF
厂商: Linear Technology
文件页数: 3/30页
文件大小: 0K
描述: IC OSC SILICON 1MHZ TSOT23-6
产品培训模块: TimerBlox Family Timing Devices
特色产品: TimerBlox?
标准包装: 2,500
系列: TimerBlox®
类型: 振荡器 - 硅
频率: 488Hz ~ 1MHz
电源电压: 2.25 V ~ 5.5 V
电流 - 电源: 235µA
工作温度: -40°C ~ 85°C
封装/外壳: SOT-23-6 细型,TSOT-23-6
包装: 带卷 (TR)
供应商设备封装: TSOT-23-6
安装类型: 表面贴装
配用: DC1562A-A-ND - BOARD EVAL LTC6990
LTC6990
11
6990fc
For more information www.linear.com/LTC6990
Table 1. DIVCODE Programming
DIVCODE
Hi-Z
NDIV
Recommended fOUT
R1 (k)
R2 (k)
VDIV/V+
0
1
62.5kHz to 1MHz
Open
Short
≤ 0.03125 ±0.015
1
0
2
31.25kHz to 500kHz
976
102
0.09375 ±0.015
2
0
4
15.63kHz to 250kHz
976
182
0.15625 ±0.015
3
0
8
7.813kHz to 125kHz
1000
280
0.21875 ±0.015
4
0
16
3.906kHz to 62.5kHz
1000
392
0.28125 ±0.015
5
0
32
1.953kHz to 31.25kHz
1000
523
0.34375 ±0.015
6
0
64
976.6Hz to 15.63kHz
1000
681
0.40625 ±0.015
7
0
128
488.3Hz to 7.813kHz
1000
887
0.46875 ±0.015
8
1
128
488.3Hz to 7.813kHz
887
1000
0.53125 ±0.015
9
1
64
976.6Hz to 15.63kHz
681
1000
0.59375 ±0.015
10
1
32
1.953kHz to 31.25kHz
523
1000
0.65625 ±0.015
11
1
16
3.906kHz to 62.5kHz
392
1000
0.71875 ±0.015
12
1
8
7.813kHz to 125kHz
280
1000
0.78125 ±0.015
13
1
4
15.63kHz to 250kHz
182
976
0.84375 ±0.015
14
1
2
31.25kHz to 500kHz
102
976
0.90625 ±0.015
15
1
62.5kHz to 1MHz
Short
Open
≥ 0.96875 ±0.015
OPERATION
Table 1 offers recommended 1% resistor values that ac-
curately produce the correct voltage division as well as the
corresponding NDIVandHi-Zvaluesfortherecommended
resistor pairs. Other values may be used as long as:
1. The VDIV/V+ ratio is accurate to ±1.5% (including resis-
tor tolerances and temperature effects)
2. Thedrivingimpedance(R1||R2)doesnotexceed500k.
If the voltage is generated by other means (i.e. the output
of a DAC) it must track the V+ supply voltage. The last
column in Table 1 shows the ideal ratio of VDIV to the
supply voltage, which can also be calculated as:
VDIV
V+
=
DIVCODE
+ 0.5
16
± 1.5%
Forexample,ifthesupplyis 3.3VandthedesiredDIVCODE
is 4, VDIV = 0.281 3.3V = 928mV ± 50mV.
Figure 2 illustrates the information in Table 1, showing
that NDIV is symmetric around the DIVCODE midpoint.
On start-up, the DIV pin A/D converter must determine
the correct DIVCODE before the output is enabled. If VDIV
0.5V+
f OUT
(kHz)
6990 F02
1000
100
10
1
0.1
INCREASING VDIV
V+
0V
RECOMMENDED RANGE
EXTENDED RANGE
Hi-Z BIT = 0
Hi-Z BIT = 1
0
15
1
3
2
5
4
7
6
9
8
11
10
13
12
14
Figure 2. Frequency Range and Hi-Z Bit vs DIVCODE
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