参数资料
型号: LTM8052IV#PBF
厂商: LINEAR TECHNOLOGY CORP
元件分类: 稳压器
英文描述: SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PBGA81
封装: 15 X 11.25 MM, 2.82 MM HEIGHT, ROHS COMPLIANT, MO-222, LGA-81
文件页数: 11/28页
文件大小: 350K
代理商: LTM8052IV#PBF
LTM8052
19
8052f
applicaTions inForMaTion
No Output Current Sharing
The LTM8052 is a two quadrant device, able to both sink
and source current to maintain voltage regulation. It is
therefore not suitable for current sharing.
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8052. The LTM8052 is neverthe-
less a switching power supply, and care must be taken to
minimize EMI and ensure proper operation. Even with the
high level of integration, you may fail to achieve specified
operation with a haphazard or poor layout. See Figure 6
for a suggested layout. Ensure that the grounding and
heat sinking are acceptable.
A few rules to keep in mind are:
1. Place the RADJ and RT resistors as close as possible to
their respective pins.
2. Place the CIN capacitor as close as possible to the VIN
and GND connection of the LTM8052.
CTL_T
CTL_I
V REF
COMP
SS
ADJ
SYNC
VIN
VIN
8052 F06
GND
CIN
VOUT
COUT
GND
THERMAL AND INTERCONNECT VIAS
RUN
RT
3. Place the COUT capacitor as close as possible to the
VOUT and GND connection of the LTM8052.
4. Place the CIN and COUT capacitors such that their
ground currents flow directly adjacent or underneath
the LTM8052.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8052.
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figure 6. The LTM8052 can benefit from
the heat sinking afforded by vias that connect to internal
GND planes at these locations, due to their proximity
to internal power handling components. The optimum
number of thermal vias depends upon the printed
circuit board design. For example, a board might use
very small via holes. It should employ more thermal
vias than a board that uses larger holes.
Figure 6. Layout Showing Suggested External Components,
GND Plane and Thermal Vias.
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